Datasheet ADL5567 (Analog Devices) - 5

Data Sheet ADL5567 SPECIFICATIONS
Supply voltage (VS) = 3.3 V or 5 V, high performance (HP) mode, output common-mode voltage (VCOM) = VS/2, source impedance (RS) = 100 Ω differential, load impedance (RL) = 200 Ω differential, output voltage (VOUT) = 2 V p-p, frequency = 200 MHz, TA = 25°C, parameters specified for differential input and differential output, signal spacing = 2 MHz for two-tone measurements, unless otherwise noted.
Table 1. Test Conditions/ VS = 3.3 V VS = 5 V Parameter Comments Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth VOUT ≤ 0.5 V p-p 4.3 4.3 GHz Bandwidth, 0.1 dB Flatness VOUT ≤ 1.0 V p-p 410 420 MHz Voltage Gain (AV) Differential Input RL = open 20 20 dB RL = 200 Ω differential 19 19 dB Single-Ended Input RL = 200 Ω differential 18 18 dB Gain Accuracy ±0.2 ±0.2 dB Channel to Channel Gain Error Frequency = 500 MHz, 0.04 0.04 dB Channel A to Channel B Channel to Channel Phase Error Frequency = 500 MHz, 0.6 0.6 Degrees Channel A to Channel B Gain Supply Sensitivity VS ± 5% 7.1 13.9 mdB/V Gain Temperature Sensitivity TA = −40°C to +85°C 1.5 1.3 mdB/°C Slew Rate Rising, VOUT = 2 V step 18 19 V/ns Falling, VOUT = 2 V step 19 20 V/ns Settling Time 2 V step to 1% 380 380 ps Overdrive Recovery Time Differential input voltage 6 4 ns step from 2 V to 0 V, for VOUT ≤ ±10 mV Reverse Isolation (SDD12) 57 57 dB Input to Output Isolation When 100 MHz; ENBLx = low 58 58 dB Disabled Channel to Channel Isolation Channel A to Channel B 69 69 dB INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Range 1.2 1.8 1.3 3.5 V Input Resistance Differential 100 100 Ω Single-Ended 91.7 91.7 Ω Input Capacitance (Single-Ended) 0.25 0.25 pF Common-Mode Rejection Ratio Frequency = 500 MHz 48 48 dB (CMRR) Output Common-Mode Range VCOM1 and VCOM2 pins 1.25 1.8 1.25 3 V Output Common-Mode Offset Referenced to VCOM (VS/2) −25 ±7 +25 −25 ±8 +40 mV Output Common-Mode Drift TA = −40°C to +85°C 1.61 1.42 mV/°C Output Differential Offset Voltage −20 ±8 +20 −20 ±8 +20 mV Output Differential Offset Drift TA = −40°C to +85°C ±15 ±6 µV/°C Output Resistance (Differential) 10 10 Ω Maximum Output Voltage Swing 1 dB compressed 5.4 8.6 V p-p POWER INTERFACE Supply Voltage 3.15 3.3 3.45 4.75 5 5.25 V Digital Input Voltage Logic High (VIH) ENBL1/ENBL2, PM1/PM2 2.1 3.45 2.1 3.45 V Logic Low (VIL) 0 1.0 0 1.0 V ENBL1/ENBL2 Input Current ENBLx = 3 V −7 −7 µA ENBLx = 0 V −70 −70 µA PM1/PM2 Input Current PMx = 3 V 62 62 µA PMx = 0 V −0.1 −0.1 µA Rev. 0 | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS INPUT AND OUTPUT INTERFACING Single-Ended Input to Differential Output INPUT AND OUTPUT EQUIVALENT CIRCUITS GAIN ADJUSTMENT AND INTERFACING EFFECT OF LOAD CAPACITANCE ADC INTERFACING SOLDERING INFORMATION AND RECOMMENDED LAND PATTERN EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE