Datasheet AD5381 (Analog Devices) - 5

AD5381 Data Sheet GENERAL DESCRIPTION
The AD5381 is a complete, single-supply, 40-channel, 12-bit An input register fol owed by a DAC register provides double denseDAC® available in a 100-lead LQFP package. Al 40 channels buffering, al owing the DAC outputs to be updated have an on-chip output amplifier with rail-to-rail operation. independently or simultaneously using the LDAC input. The AD5381 includes a programmable internal 1.25 V/2.5 V, Each channel has a programmable gain and offset adjust 10 ppm/°C reference, an on-chip channel monitor function that register that allows the user to fully calibrate any DAC chan- multiplexes the analog outputs to a common MON_OUT pin nel. Power consumption is typical y 0.25 mA/channel with for external monitoring, and an output amplifier boost mode, boost mode disabled. which al ows optimization of the amplifier slew rate. The AD5381 contains a double-buffered paral el interface featuring 20 ns WR pulse width, an SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface with interface speeds in excess of 30 MHz, and an I2C- compatible interface that supports a 400 kHz data transfer rate. Rev. E | Page 4 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide