Datasheet AD5383 (Analog Devices) - 5

AD5383 Data Sheet GENERAL DESCRIPTION
The AD5383 is a complete, single-supply, 32-channel, 12-bit An input register fol owed by a DAC register provides double denseDAC® available in a 100-lead LQFP package. Al 32 channels buffering, al owing the DAC outputs to be updated independently have an on-chip output amplifier with rail-to-rail operation. or simultaneously using the LDAC input. The AD5383 includes a programmable internal 1.25 V/2.5 V, Each channel has a programmable gain and offset adjust register 10 ppm/°C reference; an on-chip channel monitor function that that al ows the user to fully calibrate any DAC channel. With multiplexes the analog outputs to a common MON_OUT pin boost off, power consumption is typical y 0.25 mA/channel. for external monitoring; and an output amplifier boost mode that al ows optimization of the amplifier slew rate. The AD5383 features • Double-buffered paral el interface with a 20 ns WR pulse width. • SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface with interface speeds in excess of 30 MHz. • I2C-compatible interface that supports a 400 kHz data transfer rate. Rev. D | Page 4 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5383-5 Specifications AD5383-3 Specifications AC Characteristics9F Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5383 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB11 to DB0 Microprocessor Interfacing Parallel Interface AD5383 to MC68HC11 AD5383 to PIC16C6x/7x AD5383 to 8051 AD5383 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Channel Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing the FIFO Outline Dimensions Ordering Guide