Datasheet AD9142 (Analog Devices)

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9142 FEATURES GENERAL DESCRIPTION Very small inherent latency variation: <2 DAC clock cycles
The AD9142 is a dual, 16-bit, high dynamic range digital-to-
Proprietary low spurious and distortion design
analog converter (DAC) that provides a sample rate of 1600 MSPS,
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
permitting a multicarrier generation up to the Nyquist frequency.
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
The AD9142 TxDAC+® includes features optimized for direct
Flexible 16-bit LVDS interface
conversion transmit applications, including complex digital mod-
Supports word and byte load
ulation, input signal power detection, and gain, phase, and offset
Multiple chip synchronization
compensation. The DAC outputs are optimized to interface
Fixed latency and data generator latency compensation
seamlessly with analog quadrature modulators, such as the
Selectable 2×, 4×, 8× interpolation filter
ADL537x F-MOD series and the ADRF670x series from Analog
Low power architecture
Devices, Inc. A 3-wire serial port interface provides for the pro-
fS/4 power saving coarse mixer
gramming/readback of many internal parameters. Ful -scale
Input signal power detection
output current can be programmed over a range of 9 mA to 33 mA.
Emergency stop for downstream analog circuitry
The AD9142 is available in a 72-lead LFCSP.
protection PRODUCT HIGHLIGHTS FIFO error detection On-chip numeric control oscillator allows carrier placement
1. Advanced low spurious and distortion design techniques
anywhere in the DAC Nyquist bandwidth
provide high quality synthesis of wideband signals from
Transmit enable function for extra power saving
baseband to high intermediate frequencies.
High performance, low noise PLL clock multiplier
2. Very small inherent latency variation simplifies both software
Digital gain and phase adjustment for sideband suppression
and hardware design in the system. It allows easy multichip
Digital inverse sinc filter
synchronization for most applications.
Supports single DAC mode
3. New low power architecture improves power efficiency
Low power: 2.0 W at 1.6 GSPS, 1.7 W at 1.25 GSPS, full
(mW/MHz/channel) by 30%.
operating conditions
4. Input signal power and FIFO error detection simplify
72-lead LFCSP
designs for downstream analog circuitry protection.
APPLICATIONS
5. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.
Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Product Highlights Revision History Functional Block Diagram Specifications DC Specifications Digital Specifications DAC Latency Specifications Latency Variation Specifications0F AC Specifications Operating Speed Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Serial Port Operation Data Format Serial Port Pin Descriptions Serial Port Options Data Interface LVDS Input Data Ports Word Interface Mode Byte Interface Mode Data Interface Configuration Options LVDS Input Level Requirements Interface Delay Line Interface Timing Requirements SPI Sequence to Enable Delay Line-Based Mode FIFO Operation Resetting the FIFO Serial Port Initiated FIFO Reset Frame Initiated FIFO Reset Monitoring the FIFO Status Digital Datapath Interpolation Filters 2× Interpolation Mode 4× Interpolation Mode 8× Interpolation Mode Digital Modulation fS/4 Modulation NCO Modulation Updating the Frequency Tuning Word SPI Initiated Update Frame Initiated Update Datapath Configuration Digital Quadrature Gain and Phase Adjustment Quadrature Gain Adjustment Quadrature Phase Adjustment DC Offset Adjustment Inverse Sinc Filter Input Signal Power Detection and Protection Transmit Enable Function Digital Function Configuration Multidevice Synchronization and Fixed Latency Very Small Inherent Latency Variation Further Reducing the Latency Variation Set Up and Hold Timing Requirement Synchronization Implementation Synchronization Procedures Synchronization Procedure for PLL Off Synchronization Procedure for PLL On Interrupt Request Operation Interrupt Working Mechanism Interrupt Service Routine Temperature Sensor DAC Input Clock Configurations Driving the DACCLK and REFCLK Inputs Direct Clocking Clock Multiplication PLL Settings Configuring the VCO Tuning Band Automatic VCO Band Select Manual VCO Band Select Automatic Mode Sequence Manual Mode Analog Outputs Transmit DAC Operation Transmit DAC Transfer Function Transmit DAC Output Configurations Interfacing to Modulators Baseband Filter Implementation Reducing LO Leakage and Unwanted Sidebands Example Start-Up Routine Device Configuration and Start-Up Sequence Derived PLL Settings Derived NCO Settings Start-Up Sequence Device Configuration Register Map and Description SPI Configure Register Power-Down Control Register Interrupt Enable0 Register Interrupt Enable1 Register Interrupt Flag0 Register Interrupt Flag1 Register Interrupt Select0 Register Interrupt Select1 Register DAC Clock Receiver Control Register Ref Clock Receiver Control Register PLL Control Register PLL Control Register PLL Control Register PLL Status Register PLL Status Register IDAC FS Adjust LSB Register IDAC FS Adjust MSB Register QDAC FS Adjust LSB Register QDAC FS Adjust MSB Register Die Temperature Sensor Control Register Die Temperature LSB Register Die Temperature MSB Register Chip ID Register Interrupt Configuation Register Sync CTRL Register Frame Reset CTRL Register FIFO Level Configuration Register FIFO Level Readback Register FIFO CTRL Register Data Format Select Register Datapath Control Register Interpolation Control Register Over Threshold CTRL0 Register Over Threshold CTRL1 Register Over Threshold CTRL2 Register Input Power Readback LSB Register Input Power Readback MSB Register NCO Control Register NCO_FREQ_TUNING_WORD0 Register NCO_FREQ_TUNING_WORD1 Register NCO_FREQ_TUNING_WORD2 Register NCO_FREQ_TUNING_WORD3 Register NCO_PHASE_OFFSET0 Register NCO_PHASE_OFFSET1 Register IQ_PHASE_ADJ0 Register IQ_PHASE_ADJ1 Register IDAC_DC_OFFSET0 Register IDAC_DC_OFFSET1 Register QDAC_DC_OFFSET0 Register QDAC_DC_OFFSET1 Register IDAC_GAIN_ADJ Register QDAC_GAIN_ADJ Register Gain Step Control0 Register Gain Step Control1 Register TX Enable Control Register DAC Output Control Register Data Receiver Test Control Register Data Receiver Test Control Register Device Configuration0 Register Version Register Device Configuration1 Register Device Configuration2 Register DAC Latency and System Skews DAC Latency Variations FIFO Latency Variation Clock Generation Latency Variation Correcting System Skews Packaging and Ordering Information Outline Dimensions Ordering Guide