Datasheet AD7821 (Analog Devices) - 8

AD7821 CIRCUIT INFORMATION
As a result, the analog input (VIN) of the device can easily be set
BASIC DESCRIPTION
up to provide both unipolar and bipolar operation. The data The AD7821 uses a half flash conversion technique (see Func- output code for unipolar and bipolar operation is Natural Binary tional Block Diagram), whereby two 4-bit flash ADCs are used to and Offset Binary, respectively. achieve an 8-bit result. Each 4-bit flash ADC contains 15 The span of the analog input voltage can easily be varied. By comparators, which compare an unknown input voltage to the reducing the reference span, VREF(+) – VREF(–), to less than 5 V, reference ladder, to achieve a 4-bit result. The MS (most signifi- the sensitivity of the converter can be increased (i.e., if VREF = 2 V cant) flash ADC converts an unknown analog input voltage (VIN) then 1 LSB = 7.8 mV). The reference flexibility also allows the to provide the 4 MS data bits. An internal DAC, driven by the 4 MS input span for unipolar operation to be offset from zero (VREF(–) > data bits, then recreates an analog approximation of the input GND). Additionally, the input/reference arrangement facilitates voltage. The DAC output voltage is subtracted from the analog ratiometric operation. input, and the difference is converted by the LS (least significant) ADC to provide the 4 LS data bits. The MS flash ADC also has one Figures 4 and 5 show some configurations that are possible. For additional comparator to detect over-range on the analog input. minimum noise, a 47 µF capacitor in parallel with a 0.1 µF ca- pacitor should be connected between the reference inputs and GND.
OPERATING SEQUENCE
The AD7821 has two operating modes. The RD mode allows a con- version to be started and data to be read with a single, extended, READ operation (i.e., CS and RD are taken low). The conversion process is timed out by internal one-shots. The WR-RD mode uses WR to start a conversion and RD to read the data and allows the conversion timing to be externally controlled. The operating sequence for the WR-RD mode is shown in Figure 3. Figure 4. Power Supply as Reference; Unipolar Operation (0 to + 5 V) Figure 3. Operating Sequence (WR-RD Mode) A conversion is initiated and the analog input signal (VIN) sampled on the falling edge of WR (falling edge of RD, RD mode). A setup time (tP, delay time between conversions) of 350 ns is required prior to this falling edge. See the Digital Interface section for more details. When WR is low, the internal MS (most significant) ADC compares the sampled analog input with the reference ladder to provide the 4 MS data bits. A minimum of 250 ns is required for this comparison. On the rising edge of WR, the MS data result is latched internally and the LS (least significant) conversion begins, to yield the 4 LS data bits. INT goes low typically 380 ns after the rising edge of WR. This indicates the LS conversion is complete and that both the LS and MS data results are latched into the output buffer. RD going low then enables the output data. If a faster conversion time is required, the RD line can be brought low Figure 5. External Reference; 250 ns after WR goes high. This latches both the LS and MS Bipolar Operation (–2.5 V to +2.5 V) data bits and outputs the conversion result on DB0–DB7.
INPUT CURRENT REFERENCE AND INPUT
The analog input of the AD7821 behaves somewhat differently The VREF(–) and VREF(+) reference inputs on the AD7821 are than conventional ADCs. This is due to the ADC’s sampled fully differential and define the zero and full-scale input range of data comparators, which take varying amounts of input current the ADC. The transfer characteristic of the part is defined by depending on the cycle of the converter. the integer value of the following expression: The equivalent input circuit of the AD7821 is shown in Figure 6.  V −V (−)  When a conversion ends (e.g., falling edge of INT, WR-RD Data (LSBs ) = 256 IN REF V (+) − V (−) mode, t  REF REF  + 0.5 RD > tINTL) all the input switches are closed and VIN is connected to the comparators of the internal LS and MS ADCs. Therefore, VIN is simultaneously connected to 31 input capacitors of 1 pF each. REV. B –7– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS Test Circuits ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY LEAST SIGNIFICANT BIT (LSB) TOTAL UNADJUSTED ERROR SLEW RATE TOTAL HARMONIC DISTORTION INTERMODULATION DISTORTION SIGNAL-TO-NOISE RATIO PEAK HARMONIC OR SPURIOUS NOISE Typical Performance Characteristics CIRCUIT INFORMATION BASIC DESCRIPTION OPERATING SEQUENCE REFERENCE AND INPUT INPUT CURRENT INPUT TRANSIENTS INHERENT TRACK-AND-HOLD SINUSOIDAL INPUTS DIGITAL SIGNAL PROCESSING APPLICATIONS SIGNAL-TO-NOISE RATIO AND DISTORTION EFFECTIVE NUMBER OF BITS INTERMODULATION DISTORTION HISTOGRAM PLOT DIGITAL INTERFACE RD Mode (MODE = 0) WR-RD Mode (MODE = 1) MICROPROCESSOR INTERFACING AD7821 – 68008 INTERFACE AD7821 – 8088 INTERFACE AD7821 – TMS32010 INTERFACE AD7821 – 8051 INTERFACE APPLYING THE AD7821 UNIPOLAR OPERATION BIPOLAR OPERATION 16-CHANNEL TELECOM A/D CONVERTER SIMULTANEOUS SAMPLING ADCS OUTLINE DIMENSIONS Revision History