Datasheet AD7821 (Analog Devices) - 4

AD7821 TIMING CHARACTERISTICS1 (VDD = +5 V
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5%, VSS = 0 V or –5 V
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5%; Unipolar or Bipolar Input Range) Limit at Limit at Limit at +25
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C TMIN, TMAX TMIN, TMAX Parameter (All Versions) (K, B Versions) (T Version) Unit Conditions/Comments
tCSS 0 0 0 ns min CS to RD/WR Setup Time tCSH 0 0 0 ns min CS to RD/WR Hold Time t 2 RDY 70 85 100 ns max CS to RDY Delay. Pull-Up Resistor 5 kΩ tCRD 700 875 975 ns max Conversion Time (RD Mode) t 3 ACC0 Data Access Time (RD Mode) tCRD + 25 tCRD + 30 tCRD + 35 ns max CL = 20 pF tCRD + 50 tCRD + 65 tCRD + 75 ns max CL = 100 pF t 2 INTH 50 – – ns typ RD to INT Delay (RD Mode) 80 85 90 ns max t 4 DH 15 15 15 ns min Data Hold Time 60 70 80 ns max tP 350 425 500 ns min Delay Time Between Conversions tWR 250 325 400 ns min Write Pulsewidth 10 10 10 µs max tRD 250 350 450 ns min Delay Time between WR and RD Pulses tREAD1 160 205 240 ns min RD Pulsewidth (WR-RD Mode, see Figure 12b) Determined by tACC1 t 3 ACC1 Data Access Time (WR-RD Mode, see Figure 12b) 160 205 240 ns max CL = 20 pF 185 235 275 ns max CL = 100 pF tRI 150 185 220 ns max RD to INT Delay t 2 INTL 380 – – ns typ WR to INT Delay 500 610 700 ns max tREAD2 65 75 85 ns min RD Pulsewidth (WR-RD Mode, see Figure 12a) Determined by tACC2 Data Access Time (WR-RD Mode, see Figure 12a) t 3 ACC2 65 75 85 ns max CL = 20 pF 90 110 130 ns max CL = 100 pF t 2 IHWR 80 100 120 ns max WR to INT Delay (Stand-Alone Operation) t 3 ID Data Access Time after INT (Stand-Alone Operation) 30 35 40 ns max CL = 20 pF 45 60 70 ns max CL = 100 pF NOTES 1Sample tested at +25°C to ensure compliance. All input control signals are specified with tRISE = tFALL = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2CL = 50 pF. 3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice.
Test Circuits ORDERING GUIDE Total Temperature Unadjusted Package Model1 Range Error (LSB) Option2
AD7821KN –40°C to +85°C ±1 max N-20 AD7821KP –40°C to +85°C ±1 max P-20A AD7821KR –40°C to +85°C ±1 max RW-20 AD7821BQ –40°C to +85°C ±1 max Q-20 a. High Z to VOH b. High Z to VOL AD7821TQ –55°C to +125°C ± 1 max Q-20 Figure 1. Load Circuits for Data Access Time Test AD7821TE –55°C to +125°C ± 1 max E-20A NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact local sales office for military data sheet. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. a. VOH to High Z b. VOL to High Z Figure 2. Load Circuits for Data Hold Time Test REV. B –3– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS Test Circuits ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY LEAST SIGNIFICANT BIT (LSB) TOTAL UNADJUSTED ERROR SLEW RATE TOTAL HARMONIC DISTORTION INTERMODULATION DISTORTION SIGNAL-TO-NOISE RATIO PEAK HARMONIC OR SPURIOUS NOISE Typical Performance Characteristics CIRCUIT INFORMATION BASIC DESCRIPTION OPERATING SEQUENCE REFERENCE AND INPUT INPUT CURRENT INPUT TRANSIENTS INHERENT TRACK-AND-HOLD SINUSOIDAL INPUTS DIGITAL SIGNAL PROCESSING APPLICATIONS SIGNAL-TO-NOISE RATIO AND DISTORTION EFFECTIVE NUMBER OF BITS INTERMODULATION DISTORTION HISTOGRAM PLOT DIGITAL INTERFACE RD Mode (MODE = 0) WR-RD Mode (MODE = 1) MICROPROCESSOR INTERFACING AD7821 – 68008 INTERFACE AD7821 – 8088 INTERFACE AD7821 – TMS32010 INTERFACE AD7821 – 8051 INTERFACE APPLYING THE AD7821 UNIPOLAR OPERATION BIPOLAR OPERATION 16-CHANNEL TELECOM A/D CONVERTER SIMULTANEOUS SAMPLING ADCS OUTLINE DIMENSIONS Revision History