Datasheet AD7701 (Analog Devices) - 9

AD7701 Offset Calibration Range
The AD7701 can perform self-calibration using the on-chip In the system calibration modes (SC2 low), the AD7701 cali- calibration microcontroller and SRAM to store calibration brates its offset with respect to the A parameters. A calibration cycle may be initiated at any time IN pin. The offset calibration range specification defines the range of voltages, expressed as a using the CAL control input. percentage of VREF, that the AD7701 can accept and still accu- Other system components may also be included in the calibra- rately calibrate offset. tion loop to remove offset and gain errors in the input channel.
Full-Scale Calibration Range
For battery operation, the AD7701 also offers a standby mode This is the range of voltages that the AD7701 can accept in the that reduces idle power consumption to typically 10 µW. system calibration mode and still correctly calibrate full scale.
Input Span THEORY OF OPERATION
In system calibration schemes, two voltages applied in sequence The general block diagram of a sigma-delta ADC is shown in to the AD7701’s analog input define the analog input range. Figure 8. It contains the following elements: The input span specification defines the minimum and maxi- 1. A sample-hold amplifier mum input voltages from zero to full scale that the AD7701 can 2. A differential amplifier or subtracter accept and still accurately calibrate gain. The input span is 3. An analog low-pass filter expressed as a percentage of VREF. 4. A 1-bit A/D converter (comparator) 5. A 1-bit DAC
GENERAL DESCRIPTION
6. A digital low-pass filter The AD7701 is a 16-bit A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, In operation, the analog signal sample is fed to the subtracter, low frequency signals such as those representing chemical, along with the output of the 1-bit DAC. The filtered difference physical, or biological processes. It contains a charge-balancing signal is fed to the comparator, whose output samples the differ- (sigma-delta) ADC, calibration microcontroller with on-chip ence signal at a frequency many times that of the analog signal static RAM, clock oscillator, and serial communications port. sampling frequency (oversampling). The analog input signal to the AD7701 is continuously sampled
S/H AMP
at a rate determined by the frequency of the master clock, CLKIN.
COMPARATOR ANALOG
A charge-balancing A/D converter (sigma-delta modulator)
LOW-PASS FILTER DIGITAL
converts the sampled signal into a digital pulse train whose duty
FILTER
cycle contains the digital information. A six-pole Gaussian digi- tal low-pass filter processes the output of the modulator and
DIGITAL DATA DAC
updates the 16-bit output register at a 4 kHz rate. The output data can be read from the serial port randomly or periodically at any rate up to 4 kHz. Figure 8. General Sigma-Delta ADC
+5V
Oversampling is fundamental to the operation of sigma-delta
ANALOG
ADCs. Using the quantization noise formula for an ADC:
SUPPLY 0.1µF 10µF
SNR = (6.02 × number of bits + 1.76) dB
AV DV DD DD
a 1-bit ADC or comparator yields an SNR of 7.78 dB.
0.1µF VOLTAGE 2.5V SLEEP REFERENCE VREF
The AD7701 samples the input signal at 16 kHz, which spreads
MODE
the quantization noise from 0 kHz to 8 kHz. Since the specified
DRDY READ READY
analog input bandwidth of the AD7701 is only 0 Hz to 10 Hz,
CS READ RANGE
the noise energy in this bandwidth would be only 1/800 of the
BP/UP (TRANSMIT) SELECT SERIAL SCLK
total quantization noise, even if the noise energy were spread
CLOCK CALIBRATE CAL
evenly throughout the spectrum. It is reduced still further by
SDATA SERIAL DATA
analog filtering in the modulator loop, which shapes the quanti-
AD7701
zation noise spectrum to move most of the noise energy to
CLKIN ANALOG A
frequencies above 10 Hz. The SNR performance in the 0 Hz to
IN INPUT CLKOUT
10 Hz range is conditioned to the 16-bit level in this fashion. The output of the comparator provides the digital input for the
ANALOG SC2 AGND
1-bit DAC, so the system functions as a negative feedback loop
GROUND DGND 0.1µF 0.1µF
that minimizes the difference signal. The digital data that repre-
DV AV SS SS
sents the analog input voltage is in the duty cycle of the pulse
–5V
train appearing at the output of the comparator. It can be
ANALOG SUPPLY
retrieved as a parallel binary data-word using a digital filter.
0.1µF 10µF
Sigma-delta ADCs are generally described by the order of the analog low-pass filter. A simple example of a first-order, sigma- Figure 7. Typical System Connection Diagram delta ADC is shown in Figure 9. This contains only a first-order, low-pass filter or integrator. It also illustrates the derivation of the alternative name for these devices: charge-balancing ADCs. –8– REV. E Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7701 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS GROUNDING AND SUPPLY DECOUPLING ACCURACY AND AUTOCALIBRATION CALIBRATION RANGE POWER-UP AND CALIBRATION POWER SUPPLY SEQUENCING GROUNDING SINGLE-SUPPLY OPERATION SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) Asynchronous Communications (AC) Mode DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS Revision History