Datasheet AD1674 (Analog Devices) - 10

Typical Dynamic Performance–AD1674
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80 fSAMPLE = 100kSPS 0dB INPUT FULL-SCALE = +10V 70 0
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60 –20dB INPUT –20 50 THD –40 40 –60 S/(N+D) – dB 30 –80 AMPLITUDE – dB
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20 3RD –60dB INPUT –100 HARMONIC 10 –120
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2NDHARMONIC
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0 1 10 100 1000 10000 1 10 100 1000 10000 INPUT FREQUENCY – kHz INPUT FREQUENCY – kHz
Figure 5. Harmonic Distortion vs. Figure 6. S/(N+D) vs. Input Frequency Figure 7. S/(N+D) vs. Input Amplitude Input Frequency and Amplitude
0 0 –10 –20 –20 –30 –40 –40 –50 –60 –60 –70 –80 AMPLITUDE – dB –80 –100 –90 AMPLITUDE – dB –100 –120 –110 –120 –140 –130 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY – kHz FREQUENCY – kHz
Figure 8. Nonaveraged 2048 Point FFT Figure 9. IMD Plot for fIN = 9.08 kHz (fa), 9.58 kHz (fb) at 100 kSPS, fIN = 25.049 kHz DAC current sum to be greater than or less than the input cur-
GENERAL CIRCUIT OPERATION
The AD1674 is a complete 12-bit, 10 µs sampling analog-to- rent. If the sum is less, the bit is left on; if more, the bit is digital converter. A block diagram of the AD1674 is shown on turned off. After testing all the bits, the SAR contains a 12-bit page 7. binary code which accurately represents the input signal to within ± 1/2 LSB. When the control section is commanded to initiate a conversion (as described later), it places the sample-and-hold amplifier
CONTROL LOGIC
(SHA) in the hold mode, enables the clock, and resets the suc- The AD1674 may be operated in one of two modes, the full- cessive approximation register (SAR). Once a conversion cycle control mode and the stand-alone mode. The full-control mode has begun, it cannot be stopped or restarted and data is not utilizes all the AD1674 control signals and is useful in systems available from the output buffers. The SAR, timed by the inter- that address decode multiple devices on a single data bus. The nal clock, will sequence through the conversion cycle and return stand-alone mode is useful in systems with dedicated input ports an end-of-convert flag to the control section when the conver- available and thus not requiring full bus interface capability. sion has been completed. The control section will then disable Table I is a truth table for the AD1674, and Figure 10 illus- the clock, switch the SHA to sample mode, and delay the STS trates the internal logic circuitry. LOW going edge to allow for acquisition to 12-bit accuracy. The control section will allow data read functions by external
Table I. AD1674A Truth Table
command anytime during the SHA acquisition interval. During the conversion cycle, the internal 12-bit, 1 mA full-scale
CE CS R/C 12/8 A0 Operation
current output DAC is sequenced by the SAR from the most 0 X X X X None significant bit (MSB) to the least significant bit (LSB) to pro- X 1 X X X None vide an output that accurately balances the current through the 5 kΩ resistor from the input signal voltage held by the SHA. 1 0 0 X 0 Initiate 12-Bit Conversion The SHA’s input scaling resistors divide the input voltage by 2 1 0 0 X 1 Initiate 8-Bit Conversion for the 10 V input span and by 4 V for the 20 V input span, 1 0 1 1 X Enable 12-Bit Parallel Output maintaining a 1 mA full-scale output current through the 5 kΩ 1 0 1 0 0 Enable 8 Most Significant Bits resistor for both ranges. The comparator determines whether 1 0 1 0 1 Enable 4 LSBs +4 Trailing Zeroes the addition of each successively weighted bit current causes the REV. C –9–