Datasheet AD7703 (Analog Devices) - 6

AD7703 CS CS t t15 10 HI-Z HI-Z DATA DATA SDATA SDATA VALID VALID
Figure 4. SSC Mode Data Hold Time Figure 5b. SEC Mode Data Hold Time
CLKIN DRDY CS t CS 7 t8 t HI-Z HI-Z 12 SCLK t11 t t 9 SCLK 4 t8 t13 t t 5 t14 16 HI-Z HI-Z HI-Z HI-Z SDATA DB19 DB18 SDATA DB1 DB19 DB0 DB18 DB1 DB0
Figure 5a. SEC Mode Timing Diagram Figure 6. SSC Mode Timing Diagram
DEFINITION OF TERMS Positive Full-Scale Overrange Linearity Error
Positive full-scale overrange is the amount of overhead available This is the maximum deviation of any code from a straight line to handle input voltages greater than +VREF (for example, noise passing through the endpoints of the transfer function. The peaks or excess voltages due to system gain errors in system endpoints of the transfer function are zero-scale (not to be calibration routines) without introducing errors due to overloading confused with bipolar zero), a point 0.5 LSB below the first code the analog modulator or overflowing the digital filter. transition (000 . 000 to 000 . 001) and full-scale, a point
Negative Full-Scale Overrange
1.5 LSB above the last code transition (111 . 110 to 111 . This is the amount of overhead available to handle voltages below 111). The error is expressed as a percentage of full scale. –VREF without overloading the analog modulator or overflowing
Differential Linearity Error
the digital filter. Note that the analog input will accept negative This is the difference between any code’s actual width and the voltage peaks even in the Unipolar mode. ideal (1 LSB) width. Differential linearity error is expressed in
Offset Calibration Range
LSB. A differential linearity specification of ± 1 LSB or less In the system calibration modes (SC2 low), the AD7703 calibrates guarantees monotonicity. its offset with respect to the AIN pin. The offset calibration range
Positive Full-Scale Error
specification defines the range of voltages, expressed as a Positive full-scale error is the deviation of the last code transition percentage of VREF, that the AD7703 can accept and still accurately (111 . 110 to 111 . 111) from the ideal (VREF ± 3/2 LSB). calibrate offset. It applies to both positive and negative analog input ranges and
Full-Scale Calibration Range
is expressed in microvolts. This is the range of voltages that the AD7703 can accept in the
Unipolar Offset Error
system calibration mode and still correctly calibrate full scale. Unipolar offset error is the deviation of the first code transition
Input Span
from the ideal (AGND + 0.5 LSB) when operating in the In system calibration schemes, two voltages applied in sequence Unipolar mode. to the AD7703’s analog input define the analog input range. The
Bipolar Zero Error
input span specification defines the minimum and maximum This is the deviation of the midscale transition (0111 . 111 to input voltages from zero to full scale that the AD7703 can accept 1000 . 000) from the ideal (AGND – 0.5 LSB) when operating and still accurately calibrate gain. The input span is expressed in the Bipolar mode. It is expressed in microvolts. as a percentage of VREF.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal (–VREF + 0.5 LSB) when operating in the Bipolar mode. REV. E –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DEFINITION OF TERMS Linearity Error Differential Linearity Error Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span PIN CONFIGURATION DIP, CERDIP, SOIC PIN FUNCTION DESCRIPTIONS GENERAL DESCRIPTION THEORY OF OPERATION DIGITAL FILTERING FILTER CHARACTERISTICS USING THE AD7703 SYSTEM DESIGN CONSIDERATIONS CLOCKING ANALOG INPUT RANGES ACCURACY AUTOCALIBRATION Initiating Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations INPUT SIGNAL CONDITIONING Source Resistance Antialias Considerations VOLTAGE REFERENCE CONNECTIONS POWER SUPPLIES AND GROUNDING SLEEP MODE DIGITAL INTERFACE Synchronous Self-Clocking Mode (SSC) Synchronous External Clock Mode (SEC) DIGITAL NOISE AND OUTPUT LOADING OUTLINE DIMENSIONS REVISION HISTORY