Datasheet AD7712 (Analog Devices) - 8

AD7712 PIN FUNCTION DESCRIPTION Pin Mnemonic Function
1 SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when the device has completed transmission of an output word. When MODE is low, the device is in its external clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7712 in smaller batches of data. 2 MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz. 3 MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. 4 A0 Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers. 5 SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets the nodes of the digital filter. 6 MODE Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its external clocking mode. 7 AIN1(+) Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source that can be used to check that an external transducer has burned out or gone open circuit. This output current source can be turned on/off via the control register. 8 AIN1(–) Analog Input Channel 1. Negative input of the programmable gain differential analog input. 9 STANDBY Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power consumption to less than 50 µW. 10 TP Test Pin. Used when testing the device. Do not connect anything to this pin. 11 VSS Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1 should not go > 30 mV negative w.r.t. VSS for correct operation of the device. 12 AVDD Analog Positive Supply Voltage, 5 V to 10 V. 13 VBIAS Input Bias Voltage. This input voltage should be set such that VBIAS + 0.85 ⫻ VREF < AVDD and VBIAS – 0.85 ⫻ VREF > VSS where VREF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AVDD and VSS. Thus, with AVDD = +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS = –5 V, it can be tied to AGND, while with AVDD = +10 V, it can be tied to +5 V. 14 REF IN(–) Reference Input. The REF IN(–) can lie anywhere between AVDD and VSS provided REF IN(+) is greater than REF IN(–). 15 REF IN(+) Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–). REF IN(+) can lie anywhere between AVDD and VSS. 16 REF OUT Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output that is referred to AGND. 17 AIN2 Analog Input Channel 2. High level analog input that accepts an analog input voltage range of ± 4 ⫻ VREF/GAIN. At the nominal VREF of +2.5 V and a gain of 1, the AIN2 input voltage range is ± 10 V. 18 AGND Ground Reference Point for Analog Circuitry. 19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. REV. F –7– Document Outline ANALOG INPUT FUNCTIONS FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span Control Register (24 Bits) Filter Selection (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7712 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7712 to 8051 Interface AD7712 to 68HC11 Interface APPLICATIONS 4–20 mA LOOP OUTLINE DIMENSIONS Revision History