Datasheet AD7712 (Analog Devices) - 5

AD7712–SPECIFICATIONS Parameter A, S Versions1 Unit Conditions/Comments
POWER REQUIREMENTS Power Supply Voltages AVDD Voltage18 +5 to +10 V nom ±5% for Specified Performance DVDD Voltage19 +5 V nom ±5% for Specified Performance AVDD – VSS Voltage +10.5 V max For Specified Performance Power Supply Currents AVDD Current 4 mA max DVDD Current 4.5 mA max VSS Current 1.5 mA max VSS = –5 V Power Supply Rejection20 Rejection w.r.t. AGND; Assumes VBIAS Is Fixed Positive Supply (AVDD and DVDD)21 dB typ Negative Supply (VSS) 90 dB typ Power Dissipation Normal Mode 45 mW max AVDD = DVDD = +5 V, VSS = 0 V; Typically 25 mW Normal Mode 52.5 mW max AVDD = DVDD = +5 V, VSS = –5 V; Typically 30 mW Standby (Power-Down) Mode22 200 µW max AVDD = DVDD = +5 V, VSS = 0 V or –5 V; Typically 100 µW NOTES 18The AD7712 is specified with a 10 MHz clock for AVDD voltages of +5 V ± 5%. It is specified with an 8 MHz clock for AVDD voltages greater than 5.25 V and less than 10.5 V. Operating with AVDD voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0⬚C to 70⬚C temperature range. 19The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V. 20Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz. 21PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. These numbers can be improved (to 95 dB typ) by deriving the VBIAS voltage (via Zener diode or reference) from the AVDD supply. 22Using the hardware STANDBY pin. Standby power dissipation using the software standby bit (PD) of the Control Register is 8 mW typ. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Digital Input Voltage to DGND . –0.3 V to AVDD + 0.3 V (T Digital Output Voltage to DGND . –0.3 V to DV A = 25°C, unless otherwise noted.) DD + 0.3 V AVDD to DVDD . –0.3 V to +12 V Operating Temperature Range AVDD to VSS . –0.3 V to +12 V Commercial (A Version) . –40°C to +85°C AVDD to AGND . –0.3 V to +12 V Extended (S Version) . –55°C to +125°C AVDD to DGND . –0.3 V to +12 V Storage Temperature Range . –65°C to +150°C DVDD to AGND . –0.3 V to +6 V Lead Temperature (Soldering, 10 secs) . 300°C DVDD to DGND . –0.3 V to +6 V Power Dissipation (Any Package) to 75°C . 450 mW VSS to AGND . +0.3 V to –6 V *Stresses above those listed under Absolute Maximum Ratings may cause perma- VSS to DGND . +0.3 V to –6 V nent damage to the device. This is a stress rating only; functional operation of the AIN1 Input Voltage to AGND . V device at these or any other conditions above those listed in the operational SS – 0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . V sections of the specification is not implied. Exposure to absolute maximum rating SS – 0.3 V to AVDD + 0.3 V conditions for extended periods may affect device reliability. REF OUT to AGND . –0.3 V to AVDD
ORDERING GUIDE Model Temperature Range Package Options*
AD7712AN –40°C to +85°C N-24 AD7712AR –40°C to +85°C RW-24 AD7712AR-REEL –40°C to +85°C RW-24 AD7712AR-REEL7 –40°C to +85°C RW-24 AD7712AQ –40°C to +85°C Q-24 AD7712SQ –55°C to +125°C Q-24 EVAL-AD7712EB Evaluation Board *N = PDIP, Q = CERDIP; RW = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7712 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. F Document Outline ANALOG INPUT FUNCTIONS FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span Control Register (24 Bits) Filter Selection (FS11–FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burnout Current Bipolar/Unipolar Inputs REFERENCE INPUT/OUTPUT VBIAS Input USING THE AD7712 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7712 to 8051 Interface AD7712 to 68HC11 Interface APPLICATIONS 4–20 mA LOOP OUTLINE DIMENSIONS Revision History