Datasheet AD7893 (Analog Devices) - 8

AD7893 Track/Hold Section
The read operation consists of sixteen serial clock pulses to the The track/hold amplifier on the analog input of the AD7893 output shift register of the AD7893. After sixteen serial clock allows the ADC to accurately convert an input sine wave of full- pulses the shift register is reset and the SDATA line is three- scale amplitude to 12-bit accuracy. The input bandwidth of the stated. If there are more serial clock pulses after the sixteenth track/hold is greater than the Nyquist rate of the ADC, even clock, the shift register will be moved on past its reset state; when the ADC is operated at its maximum throughput rate of however, the shift register will be reset again on the falling edge 117 kHz (i.e., the track/hold can handle input frequencies in of the CONVST signal to ensure that the part returns to a excess of 58 kHz). known state every conversion cycle. As a result, a read operation The track/hold amplifier acquires an input signal to 12-bit accu- from the output register should not straddle across the falling racy in less than 1.5 µs. The operation of the track/hold is essen- edge of CONVST as the output shift register will be reset in the tially transparent to the user. The track/hold amplifier goes from middle of the read operation, and the data read back into the its tracking mode to its hold mode at the start of conversion microprocessor will appear invalid. (i.e., the rising edge of CONVST). The aperture time for the The throughput rate of the part can be increased by reading track/hold (i.e., the delay time between the external CONVST data during conversion. If the data is read during conversion, signal and the track/hold actually going into hold) is typically a throughput time of 6 µs (conversion time) plus 1.5 µs is 15 ns. At the end of conversion (6 µs after the rising edge of achieved. This minimum throughput time of 7.5 µs is achieved CONVST) the part returns to its tracking mode. The acquisi- with a slight reduction in performance from the AD7893. The tion time of the track/hold amplifier begins at this point. signal to (noise + distortion) number is likely to degrade by ap-
Reference Input
proximately 1.5 dB while the code flicker from the part will also The reference input to the AD7893 is a buffered on-chip with a increase (see AD7893 PERFORMANCE section). maximum reference input current of 1 µA. The part is specified Because the AD7893 is provided in an 8-pin package to mini- with a +2.5 V reference input voltage. Errors in the reference mize board space, the number of pins available for interfacing is source will result in gain errors in the AD7893’s transfer func- very limited. As a result, no status signal is provided from the tion and will add to the specified full-scale errors on the part. AD7893 to indicate when conversion is complete. In many On the AD7893-10 it will also result in an offset error injected applications, this will not be a problem as the data can be read in the attenuator stage. Suitable reference sources for the from the AD7893 during conversion or after conversion; how- AD7893 include the AD780 and AD680 precision +2.5 V ever, applications that want to achieve optimum performance references. from the AD7893 will have to ensure that the data read does not
Timing and Control Section
occur during conversion or during 600 ns prior to the rising Figure 3 shows the timing and control sequence required to ob- edge of CONVST. This can be achieved in two ways. The first tain optimum performance from the AD7893. In the sequence is to ensure in software that the read operation is not initiated shown, conversion is initiated on the rising edge of CONVST, until 6 µs after the rising edge of CONVST. This will only be and new data from this conversion is available in the output reg- possible if the software knows when the CONVST command is ister of the AD7893 6 µs later. Once the read operation has issued. The second scheme would be to use the CONVST sig- taken place, a further 600 ns should be allowed before the next nal as both the conversion start signal and an interrupt signal. rising edge of CONVST to optimize the settling of the track/ The simplest way to do this would be to generate a square wave hold amplifier before the next conversion is initiated. With the signal for CONVST with high and low times of 6 µs (see Figure serial clock frequency at its maximum of 8.33 MHz, the achiev- 4). Conversion is initiated on the rising edge of CONVST. The able throughput rate for the part is 6 µs (conversion time) plus falling edge of CONVST occurs 6 µs later and can be used as ei- 1.92 µs (read time) plus 0.6 µs (acquisition time). This results in ther an active low or falling, edge-triggered interrupt signal to a minimum throughput time of 8.52 µs (equivalent to a through- tell the processor to read the data from the AD7893. Provided put rate of 117 kHz). that the read operation is completed 600 ns before the rising edge of CONVST, the AD7893 will operate to specification.
t1 CONVST SCLK 600ns MIN tCONVERT CONVERSION IS INITIATED CONVERSION ENDS SERIAL READ READ OPERATION OUTPUT SERIAL AND TRACK/HOLD GOES 6µs LATER OPERATION SHOULD END 600ns SHIFT REGISTER IS INTO HOLD PRIOR TO NEXT RESET RISING EDGE OF CONVST
Figure 3. Timing Sequence for Optimum Performance from the AD7893 REV. E –7–