Datasheet AD7716 (Analog Devices) - 8

AD7716 PIN DESCRIPTION Pin Description
AVDD Analog Positive Supply, +5 V Nominal. This supplies +ve power to the analog modulators. AVDD & DVDD must be tied together externally. DVDD Digital Positive Supply, +5 V Nominal. This supplies +ve power to the digital filter and input/output registers. AVSS Analog Negative Supply, –5 V nominal. This supplies –ve power to the analog modulators. RESET A high pulse on this input pin synchronizes the sampling point on the four input channels. It can be used in a multichannel system to ensure simultaneous sampling. This also resets the digital interface to a known state. A0–A2 The three address input pins, A0, A1 and A2 give the device a unique address. This information is contained in the output data stream from the device. CLKIN Clock Input for External Clock. CLKOUT Clock Output which is used to generate an internal master clock by connecting a crystal between CLKOUT and CLKIN. If an external clock is used then CLKOUT is not connected. MODE This digital input determines the device interface mode. If it is hardwired low, then the Master Mode interface is enabled whereas if it is high, the Slave Mode interface is enabled. CASCIN This is an active-high, level-triggered digital input which is used to enable the output data stream. This input may be used to cascade several devices in a multichannel system. CASCOUT Digital output which goes high at the end of a complete 4-channel data transfer. This can be connected to the CASCIN of the next device in a multichannel system to ensure proper control of the data transfer. RFS Receive Frame Synchronization signal for the serial output data stream. This can be an input or output depending on the interface mode. SDATA Serial Data Input/Output Pin. SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, depending on the state of the Mode pin. DRDY Data Ready Output. A falling edge indicates that a new word is available for transmission. It will return high when 4, 32-bit words have been transmitted. It also goes high for one clock cycle, when a new word is being loaded into the output register. Data should not be read during this period. TFS Transmit Frame Sync input for programming the on-chip Control Register. DIN1 Digital Data Input. This is contained in the digital data stream sent from the device. DOUT1, DOUT2 Digital Outputs. These two digital outputs can be programmed from the on-chip Control Register. They can be used to control calibration signals at the front end. VREF Reference Input, Nominally 2.5 V. AGND Analog Ground. Ground reference for analog circuitry. DGND Digital Ground. Ground return for digital circuitry. AIN1–AIN4 Analog Input Pins. The analog input range is ± 2.5 V. REV. A –7–