Datasheet AD7892 (Analog Devices) - 5

AD7892 TIMING CHARACTERISTICS1, 2 (VDD = +5 V
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5%, AGND = DGND = 0 V, REF IN = +2.5 V) A, B S Parameter Versions Version Unit Test Conditions/Comments
tCONV 1.47 µs max Conversion Time for AD7892-3 1.6 1.68 µs max Conversion Time for AD7892-1, AD7892-2 tACQ 200 ns min Acquisition Time for AD7892-3 400 320 ns min Acquisition Time for AD7892-1, AD7892-2 Parallel Interface t1 35 45 ns min CONVST Pulsewidth t2 60 60 ns min EOC Pulsewidth t3 0 0 ns min EOC Falling Edge to CS Falling Edge Setup Time t4 0 0 ns min CS to RD Setup Time t5 35 45 ns min Read Pulsewidth t 3 6 35 40 ns max Data Access Time After Falling Edge of RD t 4 7 5 5 ns min Bus Relinquish Time After Rising Edge of RD 30 40 ns max t8 0 0 ns min CS to RD Hold Time t9 200 200 ns min RD to CONVST Setup Time Serial Interface t10 30 35 ns min RFS Low to SCLK Falling Edge Setup Time t 3 11 25 30 ns max RFS Low to Data Valid Delay t12 25 25 ns min SCLK High Pulsewidth t13 25 25 ns min SCLK Low Pulsewidth t 3 14 5 5 ns min SCLK Rising Edge to Data Valid Hold Time t 3 15 25 30 ns max SCLK Rising Edge to Data Valid Delay t16 20 30 ns min RFS to SCLK Falling Edge Hold Time t 4 17 0 0 ns min Bus Relinquish Time after Rising Edge of RFS 30 30 ns max t 4 17A 0 0 ns min Bus Relinquish Time after Rising Edge of SCLK 30 30 ns max NOTES 1Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2See Figures 2 and 3. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min. Specifications subject to change without notice.
1.6mA TO +1.6V OUTPUT PIN 50pF 200
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A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. C