Datasheet AD876 (Analog Devices) - 10

AD876
Figure 16 shows the equivalent input structure for the AD876 ance changes associated with the reference inputs. The simpli- reference pins. There is approximately 5 Ω of resistance between fied diagram of Figure 16 shows that the reference pins connect both the REFTF and REFBT pins and the reference ladder. If to a capacitor for one-half of the clock period. The size of the the force-sense connections are not used, the voltage drop capacitor is a function of the analog input voltage. across the 5 Ω resistors will result in a reduced voltage appear- The external reference must be able to maintain a low imped- ing across the ladder resistance. This reduces the input span of ance over all frequencies of interest in order to provide the charge the converter. Applying a slightly larger span between the REFTF required by the capacitance. By supplying the requisite charge, and REFBF pins compensates this error. Note that the tem- the reference voltages will be relatively constant and perfor- perature coefficients of the 5 Ω resistors are 1350 ppm. The mance will not degrade. For some reference configurations, user should consider the effects of temperature when not using voltage transients will be present on the reference lines; this a force-sense reference configuration. is particularly true during the falling edge of CLK. It is impor- tant that the reference recovers from the transients and settles to
5
V
AD876
the desired level of accuracy prior to the rising edges of CLK.
REFTF CLK
There are several reference configurations suitable for the
REFTS V1
AD876 depending on the application, desired level of accuracy,
R DACS LADDER C (V
and cost trade-offs. The simplest configuration, shown in Fig-
IN) 250
V ure 18, utilizes a resistor string to generate the reference volt-
REFBS V2 CLK
ages from the converter’s analog power supply. The 0.1 µF
5
V
REFBF
bypass capacitors effectively reduce high-frequency transients. The 10 µF capacitors act to reduce the impedances at the Figure 16. AD876 Equivalent Reference Structure REFTF and REFBF pins at lower frequencies. As input fre- quencies approach dc, the capacitors become ineffective, and Do not connect the REFTS and REFBS pins in configurations small voltage deviations will appear across the biasing resistors. that do not use a force-sense reference. Connecting the force This application can maintain 10-bit accuracy for input frequen- and sense lines together allows current to flow in the sense lines. cies above approximately 200 Hz. 8-bit applications can use this Any current allowed to flow through these lines must be negligi- circuit for input frequencies above approximately 50 Hz. bly small. Current flow causes voltage drops across the resis- tance in the sense lines. Because the internal D/As of the AD876 tap different points along the sense lines, each D/A
AD876
would receive a slightly different reference voltage if current
NC REFTS
were flowing in these wires. To avoid this undesirable condition,
140
V
(
6
1%)
leave the sense lines unconnected. Any current allowed to flow
4V +5V REFTF
through these lines must be negligibly small (<100 µA).
10
m
F 0.1
m
F 10
m
F 250
V The voltage drop across the internal resistor ladder determines
(
6
15%)
the input span of the AD876. The driving voltages required at
250
V
(
6
1%) 2V
the V1 and V2 points are respectively +4 V and +2 V. Calculate
REFBF 10
m
F 0.1
m
F
the full-scale input span from the equation
NC REFBS
Input Span (V ) = REFTS – REFBS
NC = NO CONNECT
This results in a full-scale input span of approximately +2 V Figure 18. Low Cost Reference Circuit when REFTS = +4 V and REFBS = +2 V In order to maintain the requisite 2 V drop across the internal ladder, the external This reference configuration provides the lowest cost but has reference must be capable of providing approximately 8.0 mA. several disadvantages. These disadvantages include poor dc power supply rejection and poor accuracy due to the variability The user has flexibility in determining both the full-scale span of of the internal and external resistors. the analog input and where to center this voltage. Figure 17 shows the range over which the AD876 can operate without The AD876 offers force-sense reference connections to elimi- degrading the typical performance. nate the voltage drops associated with the internal connections to the reference ladder. Figure 19 shows a suggested circuit
(1.6, 4.5) (2.5, 4.5)
using an AD826 dual, high speed op amp. This configuration
4.5
uses 3.6 V and 1.6 V reference voltages for REFT and REFB,
4.0
respectively. The connections shown in Figure 19 configure the
3.5
op amps as voltage followers.
(1.6, 3.5) (2.5, 3.5) 3.0 REFTF, REFTS 2.5 1.0 1.5 2.0 2.5 3.0 REFBF, REFBS
Figure 17. AD876 Reference Ranges While the previous issues address the dc aspects of the AD876 reference, the user must also be aware of the dynamic imped- REV. B –9–