Datasheet AD7861 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 11-Bit Resolution Simultaneous Sampling ADC |
| Páginas / Página | 7 / 7 — AD7861. DESCRIPTION OF THE REGISTERS. DIGITAL SIGNAL PROCESSOR … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 126 Kb |
| Idioma del documento | Inglés |
AD7861. DESCRIPTION OF THE REGISTERS. DIGITAL SIGNAL PROCESSOR INTERFACING. Reading Results. OUTPUT. CODE. FULL-SCALE. TRANSITION
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AD7861 DESCRIPTION OF THE REGISTERS DIGITAL SIGNAL PROCESSOR INTERFACING
VIN1, VIN2, VIN3 These registers contain the results from The AD7861 A/D converter is designed to be easily interfaced the conversion of the analog input voltages. to Analog Devices’ family of Digital Signal Processors (DSPs). AUX In the AD7861, this register contains the Figure 5 shows the interface between the AD7861 and the conversion result of the auxiliary channel ADSP-2101/2105/2115 16-bit fixed point DSP, and the ADSP- which had been selected by S0, S1. 2171 and ADSP-2181 DSP Microcomputers. FLAGOUT from the DSP is used to initiate the AD7861 conversion and is also
Reading Results
The A/D conversion results for channels VIN1, VIN2, VIN3 used in conjunction with the BUSY signal to provide an end of and AUX are stored in the VIN1, VIN2, VIN3 and AUX conversion interrupt for the DSP. With M0 and M1 tied low, registers respectively. The twos complement data is left justified the AD7861 is set up in the VIN2, VIN3 channel conversion 3/00 (rev. B) and the LSB (Data Bit 0) is set to zero. The relationship mode. By mapping the 12-bit AD7861 data bus into the top 12 – between input voltage and output coding is shown in Figure 4. bits of the DSP data bus (D12–D23), full-scale outputs from the 1.5 – AD7861 can be represented as ± 1.0 in fixed point arithmetic.
OUTPUT
The AD7861 can operate with a clock frequency in the range of
CODE FULL-SCALE
C2073a
TRANSITION
6.25 MHz to 12.5 MHz. For the ADSP-2101/2105/2115 the CLKOUT frequency is the system clock frequency. In the case
0 1 1 1 1 1 1 1 1 1 1 0
of the ADSP-2171/2181, the system clock is internally scaled, a 10 MHz system clock will result in a 20 MHz CLKOUT
FS = 5V
frequency. If CLKOUT from the ADSP-2171/2181 is above
0 0 0 0 0 0 0 0 0 0 0 0 5V LSB =
12.5 MHz, then an external clock divide down circuit will be
2048
necessary.
1 0 0 0 0 0 0 0 0 0 0 0 ADDRESS BUS 0V 2.5 5V-1LSB INPUT VOLTAGE A0–A13 ADDRESS A0–A1
Figure 4. AD7861 Transfer Function
DECODE Power Supply Connections and Setup DMS EN CS
The nominal power supply level (V
ADSP-2101/
DD) is +5 V ± 5%. The
ADSP-2105/ BUSY IRQ2
positive power supply (V
AD7861
DD) should be connected to Pins 21
ADSP-2115–12MHz
and 36. The SGND and DGND pins should be star point
FLAGOUT CONVST ADSP-2171–10MHz
connected to AGND at a point close to the AD7861.
RD RD ADSP-2181–10MHz CLKOUT CLK
Power supplies should be bypassed at the power pins using a
M0
0.1 µF capacitor. A 200 nF capacitor should also be connected
M1 D0–D23 D0–D11*
between REFIN and SGND.
DATA BUS
Figure 5. ADI Digital Signal Processor/Microcomputer Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leadless Chip Carrier (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.056 (1.42) 0.025 (0.63) 0.042 (1.07) 0.042 (1.07) 0.015 (0.38) 0.048 (1.21) 6 40 0.042 (1.07) 7 PIN 1 39 IDENTIFIER 0.050 (1.27) 0.63 (16.00) BSC
PRINTED IN U.S.A.
0.59 (14.99) 0.021 (0.53) TOP VIEW (PINS DOWN) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.020 0.040 (1.01) (0.50) 0.656 (16.66) 0.025 (0.64) R 0.650 (16.51) SQ 0.110 (2.79) 0.695 (17.65) SQ 0.085 (2.16) 0.685 (17.40)
–6– REV. B
VIN1, VIN2, VIN3 These registers contain the results from The AD7861 A/D converter is designed to be easily interfaced the conversion of the analog input voltages. to Analog Devices’ family of Digital Signal Processors (DSPs). AUX In the AD7861, this register contains the Figure 5 shows the interface between the AD7861 and the conversion result of the auxiliary channel ADSP-2101/2105/2115 16-bit fixed point DSP, and the ADSP- which had been selected by S0, S1. 2171 and ADSP-2181 DSP Microcomputers. FLAGOUT from the DSP is used to initiate the AD7861 conversion and is also
Reading Results
The A/D conversion results for channels VIN1, VIN2, VIN3 used in conjunction with the BUSY signal to provide an end of and AUX are stored in the VIN1, VIN2, VIN3 and AUX conversion interrupt for the DSP. With M0 and M1 tied low, registers respectively. The twos complement data is left justified the AD7861 is set up in the VIN2, VIN3 channel conversion 3/00 (rev. B) and the LSB (Data Bit 0) is set to zero. The relationship mode. By mapping the 12-bit AD7861 data bus into the top 12 – between input voltage and output coding is shown in Figure 4. bits of the DSP data bus (D12–D23), full-scale outputs from the 1.5 – AD7861 can be represented as ± 1.0 in fixed point arithmetic.
OUTPUT
The AD7861 can operate with a clock frequency in the range of
CODE FULL-SCALE
C2073a
TRANSITION
6.25 MHz to 12.5 MHz. For the ADSP-2101/2105/2115 the CLKOUT frequency is the system clock frequency. In the case
0 1 1 1 1 1 1 1 1 1 1 0
of the ADSP-2171/2181, the system clock is internally scaled, a 10 MHz system clock will result in a 20 MHz CLKOUT
FS = 5V
frequency. If CLKOUT from the ADSP-2171/2181 is above
0 0 0 0 0 0 0 0 0 0 0 0 5V LSB =
12.5 MHz, then an external clock divide down circuit will be
2048
necessary.
1 0 0 0 0 0 0 0 0 0 0 0 ADDRESS BUS 0V 2.5 5V-1LSB INPUT VOLTAGE A0–A13 ADDRESS A0–A1
Figure 4. AD7861 Transfer Function
DECODE Power Supply Connections and Setup DMS EN CS
The nominal power supply level (V
ADSP-2101/
DD) is +5 V ± 5%. The
ADSP-2105/ BUSY IRQ2
positive power supply (V
AD7861
DD) should be connected to Pins 21
ADSP-2115–12MHz
and 36. The SGND and DGND pins should be star point
FLAGOUT CONVST ADSP-2171–10MHz
connected to AGND at a point close to the AD7861.
RD RD ADSP-2181–10MHz CLKOUT CLK
Power supplies should be bypassed at the power pins using a
M0
0.1 µF capacitor. A 200 nF capacitor should also be connected
M1 D0–D23 D0–D11*
between REFIN and SGND.
DATA BUS
Figure 5. ADI Digital Signal Processor/Microcomputer Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leadless Chip Carrier (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.056 (1.42) 0.025 (0.63) 0.042 (1.07) 0.042 (1.07) 0.015 (0.38) 0.048 (1.21) 6 40 0.042 (1.07) 7 PIN 1 39 IDENTIFIER 0.050 (1.27) 0.63 (16.00) BSC
PRINTED IN U.S.A.
0.59 (14.99) 0.021 (0.53) TOP VIEW (PINS DOWN) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.020 0.040 (1.01) (0.50) 0.656 (16.66) 0.025 (0.64) R 0.650 (16.51) SQ 0.110 (2.79) 0.695 (17.65) SQ 0.085 (2.16) 0.685 (17.40)
–6– REV. B