Datasheet AD7721 (Analog Devices)

a
CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC AD7721 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-Bit Sigma-Delta ADC 468.75 kHz Output Word Rate (OWR) AGND AGND AV DV DD DD No Missing Codes Low-Pass Digital Filter DGND AD7721 High Speed Serial Interface DGND DSUBST Linear Phase 12-BIT A/D CONVERTER REFIN 229.2 kHz Input Bandwidth VIN1
S
-
D
FIR Power Supplies: AV MODULATOR FILTER DD, DVDD: +5 V
6
5% VIN2 Standby Mode (70
m
W) Parallel Mode (12-Bit/312.5 kHz OWR) DVAL/SYNC CS CLK RD WR DRDY STBY/DB0 SDATA/DB11 CAL/DB1 CONTROL LOGIC RFS/DB10 UNI/DB2 DB9 GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or ± 1.25 V. The analog input
DB3 DB4 SYNC/ DB6 SCLK/ DB8 DB5 DB7
is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-and- Use of a single bit DAC in the modulator guarantees excellent hold circuitry. The modulator output is processed by two finite linearity and dc accuracy. Endpoint accuracy is ensured by on- impulse response (FIR) digital filters in series. The on-chip chip calibration of offset and gain. This calibration procedure filtering reduces the external antialias requirements to first order minimizes the part’s zero-scale and full-scale errors. in most cases. Settling time for a step input is 97.07 µs while the group delay for the filter is 48.53 µs when the master clock The output data is accessed from the output register through a equals 15 MHz. serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors. The The AD7721 can be operated with input bandwidths up to serial interface operates in internal clocking (master) mode, the 229.2 kHz. The corresponding output word rate is 468.75 kHz. AD7721 providing the serial clock. The part can be operated with lower clock frequencies also. The sample rate, filter corner frequency and output word rate CMOS construction ensures low power dissipation while a will be reduced also, as these are proportional to the external power-down mode reduces the power consumption to only clock frequency. The maximum clock frequencies in parallel 100 µW. mode and serial mode are 10 MHz and 15 MHz respectively. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties
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