Datasheet AD9221, AD9223, AD9220 (Analog Devices) - 5

AD9221/AD9223/AD9220 PIN CONFIGURATION Zero Error
The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the devia-
CLK 1 28 DVDD
tion of the actual transition from that point.
(LSB) BIT 12 2 27 DVSS BIT 11 3 26 AVDD Gain Error BIT 10 4 25
The first code transition should occur at an analog value 1/2 LSB
AD9221/ AVSS BIT 9 5 24 AD9223/ VINB
above negative full scale. The last transition should occur at an
BIT 8 6 AD9220 23 VINA
analog value 1 1/2 LSB below the nominal full scale. Gain error
BIT 7 7 TOP VIEW 22 CML
is the deviation of the actual difference between first and last
8 (Not to Scale) BIT 6 21 CAPT
code transitions and the ideal difference between first and last
BIT 5 9 20 CAPB
code transitions.
BIT 4 10 19 REFCOM Temperature Drift BIT 3 11 18 VREF
The temperature drift for zero error and gain error specifies the
BIT 2 12 17 SENSE
maximum change from the initial (25°C) value to the value at
(MSB) BIT 1 13 16 AVSS
TMIN or TMAX.
OTR 14 15 AVDD Power Supply Rejection
The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with
PIN FUNCTION DESCRIPTIONS
the supply at its maximum limit.
Pin Aperture Jitter Number Mnemonic Description
Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. 1 CLK Clock Input Pin 2 BIT 12 Least Significant Data Bit (LSB)
Aperture Delay
3–12 BITS 11–2 Data Output Bit Aperture delay is a measure of the sample-and-hold amplifier 13 BIT 1 Most Significant Data Bit (MSB) (SHA) performance and is measured from the rising edge of the 14 OTR Out of Range clock input to when the input signal is held for conversion. 15, 26 AVDD 5 V Analog Supply
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
16, 25 AVSS Analog Ground S/N+D is the ratio of the rms value of the measured input signal 17 SENSE Reference Select to the rms sum of all other spectral components below the Nyquist 18 VREF Reference I/O frequency, including harmonics but excluding dc. The value for 19 REFCOM Reference Common S/N+D is expressed in decibels. 20 CAPB Noise Reduction Pin
Effective Number of Bits (ENOB)
21 CAPT Noise Reduction Pin For a sine wave, SINAD can be expressed in terms of the num- 22 CML Common-Mode Level (Midsupply) ber of bits. Using the following formula, 23 VINA Analog Input Pin (+) 24 VINB Analog Input Pin (–) N = SINAD ( – . 1 7 ) 6 / . 6 02 27 DVSS Digital Ground it is possible to get a measure of performance expressed as N, 28 DVDD 3 V to 5 V Digital Supply the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
DEFINITIONS OF SPECIFICATIONS
measured SINAD.
Integral Nonlinearity (INL) Total Harmonic Distortion (THD)
INL refers to the deviation of each individual code from a line THD is the ratio of the rms sum of the first six harmonic com- drawn from “negative full scale” through “positive full scale.” ponents to the rms value of the measured input signal and is The point used as negative full scale occurs 1/2 LSB before the expressed as a percentage or in decibels. first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured
Signal-to-Noise Ratio (SNR)
from the middle of each particular code to the true straight line. SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist
Differential Nonlinearity (DNL, No Missing Codes)
frequency, excluding the first six harmonics and dc. The value An ideal ADC exhibits code transitions that are exactly 1 LSB for SNR is expressed in decibels. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096
Spurious Free Dynamic Range (SFDR)
codes, respectively, must be present over all operating ranges. SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. REV. E –5– Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) Typical Performance Characteristics INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS Introduction SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface Op Amp Selection Guide DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 VREF Range Single-Ended or Differential Input, VCM = 2.5 V VINA Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 VREF Range Low Cost/Power Reference DIGITAL INPUTS AND OUTPUTS Digital Outputs Out Of Range (OTR) Digital Output Driver Considerations (DVDD) Clock Input and Considerations GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Supply Decoupling APPLICATIONS Direct IF Down Conversion Using the AD9220 Multichannel Data Acquisition with Autocalibration OUTLINE DIMENSIONS Revision History