Datasheet AD9057 (Analog Devices) - 8

AD9057 THEORY OF OPERATION 5V
The AD9057 combines Analog Devices’ proprietary MagAmp gray code conversion circuitry with flash converter technology to provide a high performance, low cost ADC. The design
VREF OUT 10k
⍀ architecture ensures low power, high speed, and 8-bit accuracy.
AD9057
A single-ended TTL/CMOS compatible ENCODE input controls
0.1 10k
⍀ ␮
F VREF IN
ADC timing for sampling the analog input pin and strobing the
5V
digital outputs (D7–D0). An internal voltage reference (VREF
AD8041
OUT) may be used to control ADC gain and offset or an exter-
VIN 1k
⍀
AIN (–0.5V
nal reference may be applied.
TO +0.5V)
The analog input signal is buffered at the input of the ADC and
1k
⍀ applied to a high speed track-and-hold. The track-and-hold circuit holds the analog input value during the conversion process Figure 3. DC-Coupled AD9057 (Inverted VIN) (beginning with the rising edge of the encode command). The
Voltage Reference
track-and-hold’s output signal passes through the gray code and A stable and accurate 2.5 V voltage reference is built into the flash conversion stages to generate coarse and fine digital AD9057 (VREF OUT). The reference output may be used to representations of the held analog input level. Decode logic set the ADC gain/offset by connecting VREF OUT to VREF IN. combines the multistage data and aligns the 8-bit word for The internal reference is capable of providing 300 mA of drive strobed outputs on the rising edge of the encode command. The current (for dc biasing the analog input or other user circuitry). MagAmp/Flash architecture of the AD9057 results in three Some applications may require greater accuracy, improved pipeline delays for the output data. temperature performance, or gain adjustments that cannot be obtained using the internal reference. An external voltage may
USING THE AD9057
be applied to the VREF IN with VREF OUT disconnected for
Analog Inputs
gain adjustment of up to ± 10% (the VREF IN pin is internally The AD9057 provides a single-ended analog input impedance tied directly to the ADC circuitry). ADC gain and offset will of 150 kW. The input requires a dc bias current of 6 mA (typical) vary simultaneously with external reference adjustment with a centered near 2.5 V (±10%). The dc bias may be provided by 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V reference the user or may be derived from the ADC’s internal voltage varies ADC gain by 2% and ADC input range center offset by reference. Figure 2 shows a low cost dc bias implementation 50 mV). Theoretical input voltage range versus reference input allowing the user to capacitively couple ac signals directly into voltage may be calculated from the following equations: the ADC without additional active circuitry. For best dynamic performance, the VREF OUT pin should be decoupled to VRANGE (p-p) = VREF IN/2.5 ground with a 0.1 mF capacitor (to minimize modulation of VMIDSCALE = VREF IN the reference voltage) and the bias resistor should be approxi- V mately 1 kW. A 1 kW bias resistor (± 20%) is included within TOP-OF-RANGE = VREF IN + VRANGE/2 the AD9057 and may be used to reduce application board size VBOTTOM-OF-RANGE = VREF IN – VRANGE /2 and complexity.
Digital Logic (5 V/3 V Systems)
The digital inputs and outputs of the AD9057 can easily be
5V
configured to interface directly with 3 V or 5 V logic systems. The encode and power-down (PWRDN) inputs are CMOS
VREF OUT
stages with TTL thresholds of 1.5 V, making the inputs compat- ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As
VREF IN 0.1
␮
F
with all high speed data converters, the encode signal should be
1k
⍀ clean and jitter free to prevent degradation of ADC dynamic performance.
BIAS OUT 0.1
␮
F VIN
The AD9057’s digital outputs will also interface directly with
AIN (1V p-p) AD9057
5 V or 3 V CMOS logic systems. The voltage supply pin (VDD) for these CMOS stages is isolated from the analog VD voltage supply. By varying the voltage on this supply pin, the digital Figure 2. Capacitively Coupled AD9057 output high level will change for 5 V or 3 V systems. Optimum SNR is obtained running the outputs at 3 V. Care should be Figure 3 shows typical connections for high performance dc taken to isolate the VDD supply voltage from the 5 V analog biasing using the ADC’s internal voltage reference. All compo- supply to minimize digital noise coupling into the ADC. nents may be powered from a single 5 V supply. In the example, analog input signals are referenced to ground. REV. D –7– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9057 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation APPLICATIONS Evaluation Board OUTLINE DIMENSIONS Revision History