Datasheet AD9243 (Analog Devices) - 6

AD9243 PIN DESCRIPTION
overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range.
Pin Number Name Description TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the 1 DVSS Digital Ground maximum change from the initial (+25°C) value to the value at 2, 29 AVSS Analog Ground TMIN or TMAX. 3 DVDD +5 V Digital Supply 4, 28 AVDD +5 V Analog Supply
POWER SUPPLY REJECTION
5 DRVSS Digital Output Driver Ground The specification shows the maximum change in full scale from 6 DRVDD Digital Output Driver Supply the value with the supply at the minimum limit to the value 7 CLK Clock Input Pin with the supply at its maximum limit. 8–10 NC No Connect 11 BIT 14 Least Significant Data Bit (LSB)
APERTURE JITTER
12–23 BIT 13–BIT 2 Data Output Bits Aperture jitter is the variation in aperture delay for successive 24 BIT 1 Most Significant Data Bit (MSB) samples and is manifested as noise on the input to the A/D. 25 OTR Out of Range
APERTURE DELAY
26, 27, 30 NC No Connect Aperture delay is a measure of the sample-and-hold amplifier 31 SENSE Reference Select (SHA) performance and is measured from the rising edge of the 32 VREF Reference I/O clock input to when the input signal is held for conversion. 33 REFCOM Reference Common 34, 35, 38 NC No Connect
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
40, 43, 44
RATIO
36 CAPB Noise Reduction Pin S/N+D is the ratio of the rms value of the measured input sig- 37 CAPT Noise Reduction Pin nal to the rms sum of all other spectral components below the 39 CML Common-Mode Level (Midsupply) Nyquist frequency, including harmonics but excluding dc. 41 VINA Analog Input Pin (+) The value for S/N+D is expressed in decibels. 42 VINB Analog Input Pin (–)
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
DEFINITIONS OF SPECIFICATION
ber of bits. Using the following formula,
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line N = (SINAD – 1.76)/6.02 drawn from “negative full scale” through “positive full scale.” it is possible to get a measure of performance expressed as N, The point used as “negative full scale” occurs 1/2 LSB before the effective number of bits. the first code transition. “Positive full scale” is defined as a Thus, effective number of bits for a device for sine wave inputs level 1 1/2 LSB beyond the last code transition. The deviation at a given input frequency can be calculated directly from its is measured from the middle of each particular code to the true measured SINAD. straight line.
TOTAL HARMONIC DISTORTION (THD) DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
THD is the ratio of the rms sum of the first six harmonic
CODES)
components to the rms value of the measured input signal and An ideal ADC exhibits code transitions that are exactly 1 LSB is expressed as a percentage or in decibels. apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384
SIGNAL-TO-NOISE RATIO (SNR)
codes, respectively, must be present over all operating ranges. SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
ZERO ERROR
Nyquist frequency, excluding the first six harmonics and dc. The major carry transition should occur for an analog value The value for SNR is expressed in decibels. 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
GAIN ERROR
input signal and the peak spurious signal. The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should
TWO-TONE SFDR
occur at an analog value 1 1/2 LSB below the nominal full The ratio of the rms value of either input tone to the rms value scale. Gain error is the deviation of the actual difference of the peak spurious component. The peak spurious component between first and last code transitions and the ideal differ- may or may not be an IMD product. May be reported in dBc ence between first and last code transitions. (i.e., degrades as signal level is lowered), or in dBFS (always
OVERVOLTAGE RECOVERY TIME
related back to converter full scale). Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an REV. A –5–