Datasheet AD9200 (Analog Devices) - 9

FabricanteAnalog Devices
Descripción10-Bit, 20 MSPS, 80 mW CMOS A/D Converter
Páginas / Página25 / 9 — AD9200. APPLYING THE AD9200. THEORY OF OPERATION. –12. –15. –18. SIGNAL …
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AD9200. APPLYING THE AD9200. THEORY OF OPERATION. –12. –15. –18. SIGNAL AMPLITUDE – dB. –21. –24. –27. 1.0E+6. 10.0E+6. 100.0E+6. 1.0E+9

AD9200 APPLYING THE AD9200 THEORY OF OPERATION –12 –15 –18 SIGNAL AMPLITUDE – dB –21 –24 –27 1.0E+6 10.0E+6 100.0E+6 1.0E+9

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AD9200 0 APPLYING THE AD9200 –3 THEORY OF OPERATION
The AD9200 implements a pipelined multistage architecture to
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achieve high sample rate with low power. The AD9200 distrib-
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utes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes
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the results from stage to stage. As a consequence of the distrib-
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uted conversion, the AD9200 requires a small fraction of the
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1023 comparators used in a traditional flash type A/D. A
SIGNAL AMPLITUDE – dB
sample-and-hold function within each of the stages permits the
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first stage to operate on a new input sample while the second,
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third and fourth stages operate on the three preceding samples.
–27 1.0E+6 10.0E+6 100.0E+6 1.0E+9 OPERATIONAL MODES FREQUENCY – Hz
The AD9200 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation Figure 13. Full Power Bandwidth applications, including pin compatibility with the AD876 A/D. To realize this flexibility, internal switches on the AD9200 are used to reconfigure the circuit into different modes. These modes
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are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the
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reference buffer, and the analog input. The nature of the appli-
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cation will determine which mode is appropriate: the descrip-
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tions in the following sections, as well as the Table I should
REFBS = 0.5V 5 REFTS = 2.5V
assist in picking the desired mode.
A CLOCK = 20MHz
m
0 – I B –5 –10 –15 –20 –25 0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE – V
Figure 14. Input Bias Current vs. Input Voltage
Table I. Mode Selection Input Input MODE REFSENSE Modes Connect Span Pin Pin REF REFTS REFBS Figure
TOP/BOTTOM AIN 1 V AVDD Short REFSENSE, REFTS and VREF Together AGND 18 AIN 2 V AVDD AGND Short REFTS and VREF Together AGND 19 CENTER SPAN AIN 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20 AIN 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 Differential AIN Is Input 1 1 V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29 REFTS and REFBS Are Shorted Together for Input 2 2 V AVDD/2 AGND No Connect AVDD/2 AVDD/2 External Ref AIN 2 V max AVDD AVDD No Connect Span = REFTS 21, 22 – REFBS (2 V max) AGND Short to Short to 23 VREFTF VREFBF AD876 AIN 2 V Float or AVDD No Connect Short to Short to 30 AVSS VREFTF VREFBF –8– REV. E