Datasheet AD7819 (Analog Devices) - 7

AD7819 CIRCUIT DESCRIPTION SUPPLY 2.7V TO 5.5V Converter Operation 10 F 0.1 F
The AD7819 is a successive approximation analog-to-digital
PARALLEL V
converter based around a charge redistribution DAC. The ADC
DD VREF INTERFACE DB0-DB7
can convert analog input signals in the range 0 V to VDD. Fig-
AD7819
ures 2 and 3 below show simplified schematics of the ADC.
0V TO VREF BUSY VIN
Figure 2 shows the ADC during its acquisition phase. SW2 is
INPUT C/ P RD
closed and SW1 is in Position A, the comparator is held in a
GND CS
balanced condition and the sampling capacitor acquires the sig- nal on V
CONVST
IN+. Figure 4. Typical Connection Diagram
CHARGE RESTRIBUTION Analog Input DAC SAMPLING
Figure 5 shows an equivalent circuit of the analog input struc-
CAPACITOR A V
ture of the AD7819. The two diodes, D1 and D2, provide ESD
IN CONTROL SW1 LOGIC
protection for the analog inputs. Care must be taken to ensure
B ACQUISITION SW2
that the analog input signal never exceeds the supply rails by
PHASE COMPARATOR
more than 200 mV. This will cause these diodes to become
CLOCK AGND VDD/3 OSC
forward biased and start conducting current into the substrate. 20 mA is the maximum current these diodes can conduct with- Figure 2. ADC Track Phase out causing irreversible damage to the part. The capacitor C2 is typically about 4 pF and can be primarily attributed to pin When the ADC starts a conversion, see Figure 3, SW2 will open capacitance. The resistor R1 is a lumped component made up of and SW1 will move to Position B causing the comparator to the on resistance of a multiplexer and a switch. This resistor is become unbalanced. The Control Logic and the Charge Redis- typically about 125 Ω. The capacitor C1 is the ADC sampling tribution DAC are used to add and subtract fixed amounts of capacitor and has a capacitance of 3.5 pF. charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebal-
VDD
anced the conversion is complete. The Control Logic generates the ADC output code. Figure 7 shows the ADC transfer function.
D1 R1 C1 125 3.5pF V V CHARGE IN DD/3 RESTRIBUTION C2 DAC D2 4pF CONVERT PHASE – SWITCH OPEN SAMPLING TRACK PHASE – SWITCH CLOSED CAPACITOR A VIN CONTROL SW1 LOGIC SW2 B CONVERSION
Figure 5. Equivalent Analog Input Circuit
PHASE COMPARATOR DC Acquisition Time CLOCK AGND VDD/3 OSC
The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the Figure 3. ADC Conversion Phase end of a conversion there is a settling time associated with the sampling circuit. This settling time lasts approximately 100 ns.
TYPICAL CONNECTION DIAGRAM
The analog signal on VIN is also being acquired during this Figure 4 shows a typical connection diagram for the AD7819. The settling time. The minimum acquisition time needed is approxi- parallel interface is implemented using an 8-bit data bus, the mately 100 ns. Figure 6 shows the equivalent charging circuit falling edge of CONVST brings the BUSY signal high and at for the sampling capacitor when the ADC is in its acquisition the end of conversion, the falling edge of BUSY is used to phase. R2 represents the source impedance of a buffer amplifier initiate an ISR on a microprocessor. (See Parallel Interface or resistive network, R1 is an internal multiplexer resistance and section for more details.) VREF is connected to a well decoupled C1 is the sampling capacitor. VDD pin to provide an analog input range of 0 V to VDD. When VDD is first connected the AD7819 powers up in a low current
R1 V
mode, i.e., power-down. A rising edge on the CONVST input
IN 125 R2
will cause the part to power up. (See Power-Up Times section.)
C1
If power consumption is of concern, the automatic power-down
3.5pF
at the end of a conversion should be used to improve power performance. See Power vs. Throughput Rate section of the Figure 6. Equivalent Sampling Circuit data sheet. –6– REV. B