Datasheet AD7720 (Analog Devices) - 11

AD7720 CIRCUIT DESCRIPTION A Sigma-Delta ADC 500
The AD7720 ADC employs a sigma-delta conversion technique
VIN(+) 2pF B
that converts the analog input into a digital pulse train. The
2pF
analog input is continuously sampled by a switched capacitor
A 500
modulator at twice the rate of the clock input frequency (2 ×
VIN(–) AC B
f
GROUND
MCLK). The digital data that represents the analog input is in the one’s density of the bit stream at the output of the sigma-
MCLK A B A B
delta modulator. The modulator outputs the bit stream at a data rate equal to fMCLK. Due to the high oversampling rate, which spreads the quantiza- Figure 22. Analog Input Equivalent Circuit tion noise from 0 to fMCLK/2, the noise energy contained in the Since the AD7720 samples the differential voltage across its band of interest is reduced (Figure 21a). To reduce the quanti- analog inputs, low noise performance is attained with an input zation noise further, a high order modulator is employed to circuit that provides low differential mode noise at each input. shape the noise spectrum, so that most of the noise energy is The amplifiers used to drive the analog inputs play a critical shifted out of the band of interest (Figure 21b). role in attaining the high performance available from the AD7720. When a capacitive load is switched onto the output of an op amp, the amplitude will momentarily drop. The op amp will try to correct the situation and, in the process, hits its slew rate
QUANTIZATION NOISE
limit. This nonlinear response, which can cause excessive ring-
fMCLK/2
ing, can lead to distortion. To remedy the situation, a low pass
BAND OF INTEREST
a. RC filter can be connected between the amplifier and the input to the AD7720 as shown in Figure 23. The external capacitor at each input aids in supplying the current spikes created during the sampling process. The resistor in this diagram, as well as
NOISE SHAPING
creating the pole for the antialiasing, isolates the op amp from the transient nature of the load.
fMCLK/2 BAND OF INTEREST
b.
R VIN(+)
Figure 21. Sigma-Delta ADC
C USING THE AD7720 ANALOG INPUT ADC Differential Inputs R VIN(–)
The AD7720 uses differential inputs to provide common-mode
C
noise rejection (i.e., the converted result will correspond to the differential voltage between the two inputs). The absolute volt- age on both inputs must lie between AGND and AVDD. Figure 23. Simple RC Antialiasing Circuit In the unipolar mode, the full-scale input range (VIN(+) – The differential input impedance of the AD7720 switched VIN(–)) is 0 V to VREF. In the bipolar mode configuration, the capacitor input varies as a function of the MCLK frequency, full-scale analog input range is ± VREF2/2. The bipolar mode given by the equation: allows complementary input signals. Alternatively, VIN(–) can be connected to a dc bias voltage to allow a single-ended input ZIN = 109/(8 fMCLK) kΩ on VIN(+) equal to VBIAS ± VREF2/2. Even though the voltage on the input sampling capacitors may
Differential Inputs
not have enough time to settle to the accuracy indicated by the The analog input to the modulator is a switched capacitor de- resolution of the AD7720, as long as the sampling capacitor sign. The analog input is converted into charge by highly linear charging follows the exponential curve of RC circuits, only the sampling capacitors. A simplified equivalent circuit diagram of gain accuracy suffers if the input capacitor is switched away too the analog input is shown in Figure 22. A signal source driving early. the analog input must be able to provide the charge onto the An alternative circuit configuration for driving the differential sampling capacitors every half MCLK cycle and settle to the inputs to the AD7720 is shown in Figure 24. required accuracy within the next half cycle. –10– REV. 0