Datasheet AD7731 (Analog Devices)

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Low Noise, High Throughput 24-Bit Sigma-Delta ADC AD7731 FEATURES GENERAL DESCRIPTION 24-Bit Sigma-Delta ADC
The AD7731 is a complete analog front-end for process control
16 Bits p-p Resolution at 800 Hz Output Rate
applications. The device has a proprietary programmable gain
Programmable Output Rates up to 6.4 kHz
front end that allows it to accept a range of input signal ranges,
Programmable Gain Front End
including low level signals, directly from a transducer. The sigma- 6
0.0015% Nonlinearity
delta architecture of the part consists of an analog modulator
Buffered Differential Inputs
and a low pass programmable digital filter, allowing adjustment
Programmable Filter Cutoffs
of filter cutoff, output rate and settling time.
FASTStep™* Mode for Channel Sequencing
The part features three buffered differential programmable gain
Single Supply Operation
analog inputs (which can be configured as five pseudo-differential inputs), as well as a differential reference input. The part oper-
APPLICATIONS
ates from a single +5 V supply and accepts seven unipolar ana-
Process Control
log input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV,
PLCs/DCS
+320 mV, +640 mV and +1.28 V, and seven bipolar ranges:
Industrial Instrumentation
±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V. The peak-to-peak resolution achievable directly from the part is 16 bits at an 800 Hz output rate. The part can switch between channels with 1 ms settling time and maintain a perfor- mance level of 13 bits of peak-to-peak resolution. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7731 contains self-calibration and system calibration options and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The part is available in a 24-lead plastic DIP, a 24-lead SOIC and 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN(–) REF IN(+) AD7731 NC AVDD STANDBY AIN1 SIGMA-DELTA A/D CONVERTER 100nA BUFFER AIN2 SIGMA- PROGRAMMABLE SYNC DELTA DIGITAL AIN3 MODULATOR FILTER MUX PGA AIN4 100nA AIN5 CLOCK MCLK IN AIN6 AGND SERIAL INTERFACE GENERATION MCLK OUT AND CONTROL LOGIC REGISTER BANK SCLK CALIBRATION CS MICROCONTROLLER DIN DOUT AGND DGND POL RDY RESET *
FASTStep is a trademark of Analog Devices, Inc. REV. REV. 0 A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or
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otherwise under any patent or patent rights of Analog Devices.
Fax: 617/326-8703 © Analog Devices, Inc., 1997
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM AD7731-SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ordering Guide ESD Caution PIN CONFIGURATION Pin Function Descriptions TERMINOLOGY OUTPUT NOISE AND RESOLUTION SPECIFICATION Output Noise (CHP = 0, SKIP= 1) Output Noise (CHP = 1, SKIP = 0) ON-CHIP REGISTERS Communications Register (RS2-RS0 = 0, 0, 0) Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex Offset Calibration Register (RS2-RS0 = 1, 0, 1) Gain Calibration Register (RS2-RS0 = 1, 1, 0) Test Register (RS2-RS0 = 1, 1, 1); Power On/Reset Status: 000000 Hex READING FROM AND WRITING TO THE ON-CHIP REGISTERS CALIBRATION OPERATION SUMMARY CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Channels Buffered Inputs Analog Input Ranges Programmable Gain Amplifier Bipolar/Unipolar Inputs Burnout Currents REFERENCE INPUT Reference Detect SIGMA-DELTA MODULATOR DIGITAL FILTERING Filter Architecture First State Filter/SKIP Mode Enabled (SKIP =1) Nonchop Mode (SKIP =1, CHP = 0) Chop Mode (SKIP = 1, CHP =1) Second Stage Filter Normal FIR Operation (SKIP = 0) Chop Mode (SKIP = 0, CHP =1) Nonchop Mode (SKIP = 1, CHP = 0) FASTStep Mode (SKIP = 0, FAST = 1) CALIBRATION Internal Zero-Scale Calibration Internal Full-Scale Calibration System Zero-Scale Calibration System Full-Scale Calibration Span and Offset Limits Power-Up and Calibration Drift Considerations USING THE AD7731 Clocking and Oscillator Circuit System Synchronization Single-Shot Conversions Reset Input Standby Mode Digital Outputs POWER SUPPLIES Grounding and Layout Evaluting the AD7731 Performance SERIAL INTERFACE Write Operation Read Operation CONFIGURING THE AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7731 to 68HC11 Interface AD7731 to 8051 Interface AD7731 to ADSP-2103/ADSP-2105 Interface APPLICATIONS Data Acquisition Programmable Logic Controllers Pressure Measurement Temperature Measurement Bipolar Input Signals PAGE INDEX TABLE INDEX OUTLINE DIMENSIONS