Datasheet AD7730, AD7730L (Analog Devices) - 7

AD7730/AD7730L INPUT CHOPPING SINC3 FILTER SKIP MODE 22-TAP FIR FILTER THE ANALOG INPUT TO THE PART CAN BE THE FIRST STAGE OF THE DIGITAL FILTERING IN SKIP MODE, THERE IS NO SECOND IN NORMAL OPERATING MODE, THE CHOPPED. IN CHOPPING MODE, WITH ON THE PART IS THE SINC3 FILTER. THE STAGE OF FILTERING ON THE PART. THE SECOND STAGE OF THE DIGITAL FILTERING AC EXCITATION DISABLED, THE INPUT OUTPUT UPDATE RATE AND BANDWIDTH SINC3 FILTER IS THE ONLY FILTERING ON THE PART IS A FIXED 22-TAP FIR CHOPPING IS INTERNALTO THE DEVICE. IN OF THIS FILTER CAN BE PROGRAMMED. IN PERFORMED ON THE PART. FILTER. IN SKIP MODE, THIS FIR FILTER IS CHOPPING MODE, WITH AC EXCITATION SKIP MODE, THE SINC3 FILTER IS THE BYPASSED. WHEN FASTSTEP™ MODE IS ENABLED, THE CHOPPING IS ASSUMED ONLY FILTERING PERFORMED ON THE PART. ENABLED AND A STEP INPUT IS SEE PAGE 29 TO BE PERFORMED EXTERNAL TO THE PART DETECTED, THE SECOND STAGE FILTERING AND NO INTERNAL INPUT CHOPPING IS IS PERFORMED BY THE FILTER SEE PAGE 26 PERFORMED. THE INPUT CHOPPING CAN UNTIL THE OUTPUT OF THIS FILTER BE DISABLED, IF DESIRED. HAS FULLY SETTLED. SEE PAGE 26 SEE PAGE 27 SKIP PGA + 22-TAP ANALOG OUTPUT CHOP BUFFER SIGMA-DELTA SINC3 FILTER CHOP DIGITAL FIR FILTER INPUT SCALING MODULATOR OUTPUT FASTSTEP OUTPUT SCALING FILTER THE OUTPUT WORD FROM THE DIGITAL BUFFER PGA + SIGMA-DELTA MODULATOR OUTPUT CHOPPING FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED THE INPUT SIGNAL IS BUFFERED THE PROGRAMMABLE GAIN CAPABILITY THE OUTPUT OF THE FIRST STAGE AS THE CONVERSION RESULT. ON-CHIP BEFORE BEING APPLIED TO OF THE PART IS INCORPORATED OF FILTERING ON THE PART CAN THE SAMPLING CAPACITOR OF THE AROUND THE SIGMA-DELTA MODULATOR. BE CHOPPED. IN CHOPPING MODE, SEE PAGE 29 SIGMA-DELTA MODULATOR. THIS THE MODULATOR PROVIDES A HIGH- REGARDLESS OF WHETHER AC ISOLATES THE SAMPLING CAPACITOR FREQUENCY 1-BIT DATA STREAM EXCITATION IS ENABLED OR DISABLED, CHARGING CURRENTS FROM THE TO THE DIGITAL FILTER. THE OUTPUT CHOPPING IS ANALOG INPUT PINS. PERFORMED. THE CHOPPING CAN FASTSTEP FILTER BE DISABLED, IF DESIRED. SEE PAGE 26 SEE PAGE 24 WHEN FASTSTEP MODE IS ENABLED SEE PAGE 26 AND A STEP CHANGE ON THE INPUT HAS BEEN DETECTED, THE SECOND STAGE FILTERING IS PERFORMED BY THE FASTSTEP FILTER UNTIL THE FIR FILTER HAS FULLY SETTLED. SEE PAGE 29
Figure 3. Signal Processing Chain
PIN CONFIGURATION SCLK 1 24 DGND MCLK IN 2 23 DVDD MCLK OUT 3 22 DIN POL 4 21 DOUT SYNC 5 20 RDY AD7730 RESET 6 19 CS TOP VIEW VBIAS 7 (Not to Scale) 18 STANDBY AGND 8 17 ACX AVDD 9 16 ACX AIN1(+) 10 15 REF IN(–) AIN1(–) 11 14 REF IN(+) AIN2(+)/D1 12 13 AIN2(–)/D0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function
1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7730. This serial clock can be a continuous clock with all data transmitted in a con- tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the AD7730 in smaller batches of data. 2 MCLK IN Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The AD7730 is specified with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of 2.4576 MHz. REV. B –7–