Datasheet AD9201 (Analog Devices) - 10

AD9201
The AD9201 can accommodate a variety of input spans be-
AC Coupled Inputs
tween 1 V and 2 V. For spans of less than 1 V, expect a propor- If the signal of interest has no dc component, ac coupling can be tionate degradation in SNR . Use of a 2 V span will provide the easily used to define an optimum bias point. Figure 18 illus- best noise performance. 1 V spans will provide lower distortion trates one recommended configuration. The voltage chosen for when using a 3 V analog supply. Users wishing to run with the dc bias point (in this case the 1 V reference) is applied to larger full-scales are encouraged to use a 5 V analog supply both IINA and IINB pins through 1 kΩ resistors (R1 and R2). (AVDD). IINA is coupled to the input signal through Capacitor C1, while
Single-Ended Inputs:
For single-ended input signals, the IINB is decoupled to ground through Capacitor C2 and C3. signal is applied to one input pin and the other input pin is tied
Transformer Coupled Inputs
to a midscale voltage. This midscale voltage defines the center Another option for input ac coupling is to use a transformer. of the full-scale span for the input signal. This not only provides dc rejection, but also allows truly differ- EXAMPLE: For a single-ended input range from 0 V to 1 V ential drive of the AD9201’s analog inputs, which will provide applied to IINA, we would configure the converter for a 1 V the optimal distortion performance. Figure 19 shows a recom- reference (See Figure 17) and apply 0.5 V to IINB. mended transformer input drive configuration. Resistors R1 and R2 define the termination impedance of the transformer coupling. The center tap of the transformer secondary is tied to the com-
1V
mon-mode reference, establishing the dc bias point for the ana-
0V 0.1
m
F
log inputs.
INPUT IINA I OR QREFT 0.1
m
F 10
m
F MIDSCALE VOLTAGE IINB I OR QREFB = 0.5V 10
m
F 0.1 0.1
m
F
m
F IINA QINA AD9201 R1 R2 5k
V
5k
V
IINB QINB VREF REFSENSE AD9201 0.1 COMMON
m
F MODE I OR QREFT VOLTAGE 0.1
m
F 10
m
F 0.1
m
F 10
m
F VREF 10
m
F 0.1
m
F I OR QREFB 0.1
m
F REFSENSE
Figure 17. Example Configuration for 0 V–1 V Single- Ended Input Signal Figure 19. Example Configuration for Transformer Note that since the inputs are high impedance, this reference Coupled Inputs level can easily be generated with an external resistive divider
Crosstalk:
The internal layout of the AD9201, as well as its with large resistance values (to minimize power dissipation). A pinout, was configured to minimize the crosstalk between the decoupling capacitor is recommended on this input to minimize two input signals. Users wishing to minimize high frequency the high frequency noise-coupling onto this pin. Decoupling crosstalk should take care to provide the best possible decoupling should occur close to the ADC. for input pins (see Figure 20). R and C values will make a pole
Differential Inputs
dependant on antialiasing requirements. Decoupling is also Use of differential input signals can provide greater flexibility in required on reference pins and power supplies (see Figure 21). input ranges and bias points, as well as offering improvements in distortion performance, particularly for high frequency input signals. Users with differential input signals will probably want
IINA QINA
to take advantage of the differential input structure.
AD9201 IINB QINB 1.5V 0.1
m
F C1 0.5V REFT ANALOG IINA 0.1
m
F 10
m
F
Figure 20. Input Loading
INPUT R1 1k
V
REFB IINB 0.1
m
F V ANALOG V DIGITAL C2 C3 1.0
m
F 0.1
m
F AD9201 AVDD DVDD VREF 10
m
F 0.1
m
F 0.1
m
F 10
m
F REFSENSE AD9201 I OR QREFT
Figure 18. Example Configuration for 0.5 V–1.5 V ac
0.1
m
F 10
m
F 0.1
m
F
Coupled Single-Ended Inputs
I OR QREFB 0.1
m
F
Figure 21. Reference and Power Supply Decoupling REV. D –9–