Datasheet AD7705, AD7706 (Analog Devices)

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3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs AD7705/AD7706 FEATURES FUNCTIONAL BLOCK DIAGRAM AD7705: 2 fully differential input channel ADCs VDD REF IN(–) REF IN(+) AD7706: 3 pseudo differential input channel ADCs AD7705/AD7706 16 bits no missing codes CHARGE 0.003% nonlinearity BALANCING A/D CONVERTER Programmable gain front end: gains from 1 to 128 ANALOG
Σ
-
Δ
3-wire serial interface INPUT MAX BUFFER PGA MODULATOR CHANNELS SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible A = 1
≈
128 Schmitt-trigger input on SCLK DIGITAL FILTER Ability to buffer the analog input 2.7 V to 3.3 V or 4.75 V to 5.25 V operation Power dissipation 1 mW maximum @ 3 V Standby current 8 μA maximum SERIAL INTERFACE 16-lead PDIP, 16-lead SOIC, and 16-lead TSSOP packages REGISTER BANK MCLK IN CLOCK SCLK GENERATION GENERAL DESCRIPTION MCLK OUT CS DIN
The AD7705/AD7706 are complete analog front ends for low
DOUT
frequency measurement applications. These 2-/3-channel devices can accept low level input signals directly from a transducer and 001
GND DRDY RESET
01166- produce serial digital output. The devices employ a Σ-Δ conversion technique to realize up to 16 bits of no missing codes Figure 1. performance. The selected input signal is applied to a The AD7705/AD7706 devices, with a 3 V supply and a 1.225 V proprietary, programmable-gain front end based around an reference, can handle unipolar input signal ranges of 0 mV to analog modulator. The modulator output is processed by an on- 10 mV through 0 V to 1.225 V. The devices can accept bipolar chip digital filter. The first notch of this digital filter can be pro- input ranges of ±10 mV through ±1.225 V. Therefore, the grammed via an on-chip control register, allowing adjustment of AD7705/AD7706 devices perform all signal conditioning and the filter cutoff and output update rate. conversion for a 2-channel or 3-channel system. The AD7705/AD7706 devices operate from a single 2.7 V to The AD7705/AD7706 are ideal for use in smart, microcontroller, 3.3 V or 4.75 V to 5.25 V supply. The AD7705 features two fully or DSP-based systems. The devices feature a serial interface that differential analog input channels; the AD7706 features three can be configured for 3-wire operation. Gain settings, signal pseudo differential input channels. polarity, and update rate selection can be configured in software Both devices feature a differential reference input. Input signal using the input serial port. The parts contains self-calibration and ranges of 0 mV to 20 mV through 0 V to 2.5 V can be system calibration options to eliminate gain and offset errors on incorporated on both devices when operating with a V the part itself or in the system. CMOS construction ensures very DD of 5 V and a reference of 2.5 V. They can also handle bipolar input low power dissipation, and the power-down mode reduces the signal ranges of ±20 mV through ±2.5 V, which are referenced to standby power consumption to 20 μW typ. the AIN(−) inputs on the AD7705 and to the COMMON input These parts are available in a 16-lead, wide body (0.3 inch), on the AD7706. plastic dual in-line package (DIP); a 16-lead, wide body (0.3 inch), standard small outline (SOIC) package; and a low profile, 16-lead, thin shrink small outline package (TSSOP).
Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTPUT NOISE (5 V OPERATION) OUTPUT NOISE (3 V OPERATION) TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATION REGISTER (RS2, RS1, RS0 = 0, 0, 0) SETUP REGISTER (RS2, RS1, RS0 = 0, 0, 1); POWER-ON/RESET STATUS: 01 HEXADECIMAL CLOCK REGISTER (RS2, RS1, RS0 = 0, 1, 0); POWER-ON/RESET STATUS: 05 HEXADECIMAL DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1) TEST REGISTER (RS2, RS1, RS0 = 1, 0, 0); POWER-ON/RESET STATUS: 00 HEXADECIMAL ZERO-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 0); POWER-ON/RESET STATUS: 1F4000 HEXADECIMAL FULL-SCALE CALIBRATION REGISTER (RS2, RS1, RS0 = 1, 1, 1); POWER-ON/RESET STATUS: 5761AB HEXADECIMAL Calibration Sequences CIRCUIT DESCRIPTION ANALOG INPUT Ranges Sample Rate BIPOLAR/UNIPOLAR INPUT REFERENCE INPUT DIGITAL FILTERING Filter Characteristics Postfiltering ANALOG FILTERING CALIBRATION Self-Calibration System Calibration Span and Offset Limits Power-Up and Calibration THEORY OF OPERATION CLOCKING AND OSCILLATOR CIRCUIT SYSTEM SYNCHRONIZATION RESET INPUT STANDBY MODE ACCURACY DRIFT CONSIDERATIONS POWER SUPPLIES SUPPLY CURRENT GROUNDING AND LAYOUT EVALUATING THE PERFORMANCE DIGITAL INTERFACE CONFIGURING THE AD7705/AD7706 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7705/AD7706-to-68HC11 Interface AD7705/AD7706-to-8051 Interface AD7705/AD7706-to-ADSP-2103/ADSP-2105 Interface CODE FOR SETTING UP THE AD7705/AD7706 C Code for Interfacing AD7705 to 68HC11 APPLICATIONS PRESSURE MEASUREMENT TEMPERATURE MEASUREMENT SMART TRANSMITTERS BATTERY MONITORING OUTLINE DIMENSIONS ORDERING GUIDE