Datasheet AD9051 (Analog Devices) - 10

AD9051 THEORY OF OPERATION 140
⍀ Refer to the block diagram on the front page.
5V
The AD9051 employs a subranging architecture with digital
140
⍀
5V V
error correction. This combination of design techniques ensures
IN 10 –0.625V
true 10-bit accuracy at the digital outputs of the converter.
TO AD9631 AD9051 +0.625V
At the input, the analog signal is buffered by a high speed
9 0.1
␮
F
differential buffer and applied to a track-and-hold (T/H) that
5V
holds the analog value present when the unit is strobed with
1k
⍀
AD820 1k
⍀ an ENCODE command. The conversion process begins on the
0.1
␮
F
rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. Error correction and decode logic correct and align data from Figure 3. Single Supply, Single-Ended, DC-Coupled the two conversions and present the result as a 10-bit parallel AD9051 digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in
140
⍀ five pipeline delays for the output data. Refer to the AD9051 Timing Diagram.
+5V 140
⍀
5V 0.1
␮
F VIN 10 USING THE AD9051 –0.625V TO AD9631 AD9051 3 V System +0.625V –5V 9
The digital input and outputs of the AD9051 can be easily
0.1
␮
F
configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of Figure 4. Single-Ended, Capacitively-Coupled AD9051 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation with TTL, CMOS and 3 V CMOS logic families. Using 3 V
140
⍀ CMOS logic allows the user to drive the encode directly without
+5V
the need to translate to 5 V. This saves the user power and
5V 140
⍀
0.1
␮
F V
board space. As with all high speed data converters, the clock
IN T1-1T 10 –0.625V
signal must be clean and jitter free to prevent the degradation of
TO AD9631 50
⍀
AD9051 +0.625V
dynamic performance.
–5V 9
The AD9051 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer Figure 5. Differentially Driven AD9051 Using Trans- to AD9051 Output Stage) with isolated supply pins (Pins 20, former Coupling 22 VDD). By varying the voltage on the VDD pins, the digital The AD830 provides a unique method of providing dc level output levels vary respectively. By connecting Pins 20 and 22 to shift for the analog input. Using the AD830 allows a great deal the 3 V logic supply, the AD9051 will supply 3 V output of flexibility for adjusting offset and gain. Figure 6 shows the levels. Care should be taken to filter and isolate the output AD830 configured to drive the AD9051. The offset is provided supply of the AD9051 as noise could be coupled into the by the internal biasing of the AD9051 differential input (Pin 9). ADC, limiting performance. For more information regarding the AD830, see the AD830
Analog Input
data sheet. The analog input of the AD9051 is a differential input buffer (refer to AD9051 Equivalent Analog Input). The differential
+15V +5V
inputs are internally biased at 2.5 V, obviating the need for
1 VIN
external biasing. Excellent performance is achieved whether the
2 –0.625V 7 10 3 AD830
analog inputs are driven single-endedly or differentially (for
TO +0.625V 4 AD9051
best dynamic performance, impedances at AIN and AINB
–5V 9
should match). Figure 3 shows typical connections for the analog inputs when
0.1
␮
F
using the AD9051 in a dc-coupled system with single-ended signals. All components are powered from a single 5 V supply. The AD820 is used to offset the ground referenced input signal Figure 6. Level-Shifting with the AD830 to the level required by the AD9051. AC coupling of the analog inputs of the AD9051 is easily accomplished. Figure 4 shows capacitive coupling of a single- ended signal while Figure 5 shows transformer coupling differentially into the AD9051. REV. C –9–