Datasheet AD7894 (Analog Devices) - 8

AD7894 Track/Hold Section
the next falling edge of CONVST to optimize the settling of the The track/hold amplifier on the analog input of the AD7894 track/hold amplifier before the next conversion is initiated. allows the ADC to accurately convert an input sine wave of full- With the serial clock frequency at its maximum of 16␣ MHz, the scale amplitude to 14-bit accuracy. The input bandwidth of the achievable throughput rate for the part is 5␣ µs (conversion track/hold is greater than the Nyquist rate of the ADC, even time) plus 1.0␣ µs (read time) plus 250␣ ns (quiet time). This when the ADC is operated at its maximum throughput rate of results in a minimum throughput time of 6.25␣ µs (equivalent to 160 kHz (i.e., the track/hold can handle input frequencies in a throughput rate of 160 kHz). A serial clock of less than 16 MHz excess of 100 kHz). can be used, but this will in turn mean that the throughput The track/hold amplifier acquires an input signal to 14-bit accu- time will increase. racy in less than 0.35␣ µs. The operation of the track/hold is The read operation consists of 16 serial clock pulses to the essentially transparent to the user. With the high sampling output shift register of the AD7894. After 16 serial clock pulses operating mode the track/hold amplifier goes from its tracking the shift register is reset and the SDATA line is three-stated. If mode to its hold mode at the start of conversion (i.e., the falling there are more serial clock pulses after the 16th clock, the shift edge of CONVST). The aperture time for the track/hold (i.e., register will be moved on past its reset state. However, the shift the delay time between the external CONVST signal and the register will be reset again on the falling edge of the CONVST track/hold actually going into hold) is typically 15␣ ns. At the signal to ensure that the part returns to a known state every end of conversion (on the falling edge of BUSY) the part re- conversion cycle. As a result, a read operation from the output turns to its tracking mode. The acquisition time of the track/ register should not straddle across the falling edge of CONVST hold amplifier begins at this point. For the auto shutdown mode, as the output shift register will be reset in the middle of the the rising edge of CONVST wakes up the part and the track read operation and the data read back into the microprocessor and hold amplifier goes from its tracking mode to its hold mode will appear invalid. 5 µs after the rising edge of CONVST (provided that the
OPERATING MODES
CONVST high time is less than 5 µs). Once again the part re-
Mode 1 Operation (High Sampling Performance)
turns to its tracking mode at the end of conversion when the The timing diagram in Figure 3 is for optimum performance in BUSY signal goes low. operating Mode 1 where the falling edge of CONVST starts
Reference Input
conversion and puts the Track/Hold amplifier into its hold The reference input to the AD7894 is buffered on-chip with a mode. This falling edge of CONVST also causes the BUSY maximum reference input current of 1␣ µA. The part is specified signal to go high to indicate that a conversion is taking place. with a +2.5 V reference input voltage. Errors in the reference The BUSY signal goes low when the conversion is complete, source will result in gain errors in the AD7894’s transfer func- which is 5 µs max after the falling edge of CONVST and new tion and will add to the specified full-scale errors on the part. data from this conversion is available in the output register of Suitable reference sources for the AD7894 include the AD780 the AD7894. A read operation accesses this data. This read and AD680 precision +2.5 V references. operation consists of 16 clock cycles and the length of this read operation will depend on the serial clock frequency. For the
Timing and Control Section
Figure 3 shows the timing and control sequence required to fastest throughput rate (with a serial clock of 16 MHz) the read obtain optimum performance from the AD7894. In the se- operation will take 1.0 µs. The read operation must be com- quence shown, conversion is initiated on the falling edge of plete at least 250 ns before the falling edge of the next CONVST CONVST and new data from this conversion is available in the and this gives a total time of 6.25 µs for the full throughput output register of the AD7894 5␣ µs later. Once the read opera- time (equivalent to 160 kHz). This mode of operation should tion has taken place, a further 250␣ ns should be allowed before be used for high sampling applications.
t1 = 40ns MIN CONVST BUSY 250ns MIN SCLK tCONVERT = 5
m
s CONVERSION IS CONVERSION SERIAL READ READ OPERATION OUTPUT INITIATED; ENDS OPERATION SHOULD END SERIAL TRACK/HOLD 5
m
s LATER 250ns PRIOR TO SHIFT GOES INTO HOLD NEXT FALLING REGISTER EDGE OF CONVST IS RESET
Figure 3. Mode 1 Timing Operation Diagram for High Sampling Performance REV. 0 –7–