Datasheet AD7865 (Analog Devices) - 5

AD7865 (V TIMING CHARACTERISTICS1, 2 DD = 5 V 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications TMIN to TMAX unless otherwise noted.) Parameter A, B, Y Versions Unit Test Conditions/Comments
tCONV 2.4 µs max Conversion Time, Internal Clock 3.2 µs max Conversion Time, External Clock (5 MHz) tACQ 0.35 µs max Acquisition Time tBUSY No. of Channels Selected Number of Channels Multiplied by tCONV × (tCONV) µs max t 3 WAKE-UP —External VREF 1 µs max STBY Rising Edge to CONVST Rising Edge t1 35 ns min CONVST Pulsewidth t2 70 ns min CONVST Rising Edge to BUSY Rising Edge Read Operation t3 0 ns min CS to RD Setup Time t4 0 ns min CS to RD Hold Time t5 35 ns min Read Pulsewidth t 4 6 35 ns max Data Access Time after Falling Edge of RD, VDRIVE = 5 V 40 ns max Data Access Time after Falling Edge of RD, VDRIVE = 3 V t 5 7 5 ns min Bus Relinquish Time after Rising Edge of RD 30 ns max t8 15 ns min Time Between Consecutive Reads t9 120 ns min EOC Pulsewidth 180 ns max t10 70 ns max RD Rising Edge to FRSTDATA Edge (Rising or Falling) t11 15 ns max EOC Falling Edge to FRSTDATA Falling Delay t12 0 ns min EOC to RD Delay Write Operation t13 20 ns min WR Pulsewidth t14 0 ns min CS to WR Setup Time t15 0 ns min WR to CS Hold Time t16 5 ns min Input Data Setup Time of Rising Edge of WR t17 5 ns min Input Data Hold Time External Clock t18 200 ns min CONVST Falling Edge to CLK Rising Edge NOTES 1Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 6, 7 and 8. 3Refer to the Standby Mode Operation section. The MAX specification of 1 µs is valid when using a 0.1 µF decoupling capacitor on the VREF pin. 4Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 5These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
1.6mA TO OUTPUT 1.6V PIN 50pF 400 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. B