Datasheet AD7888 (Analog Devices) - 6

FabricanteAnalog Devices
Descripción2.7 V to 5.25 V, Micro Power, 8-Channel, 125 kSPS, 12-Bit ADC in 16-Pin TSSOP
Páginas / Página18 / 6 — AD7888. PIN CONFIGURATIONS. SOIC AND TSSOP. CS 1. SCLK. REF IN/REF OUT. …
RevisiónC
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AD7888. PIN CONFIGURATIONS. SOIC AND TSSOP. CS 1. SCLK. REF IN/REF OUT. DOUT. DIN. AGND. TOP VIEW. AIN1. (Not to Scale) 12 AIN8. AIN2. AIN7. AIN3

AD7888 PIN CONFIGURATIONS SOIC AND TSSOP CS 1 SCLK REF IN/REF OUT DOUT DIN AGND TOP VIEW AIN1 (Not to Scale) 12 AIN8 AIN2 AIN7 AIN3

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AD7888 PIN CONFIGURATIONS SOIC AND TSSOP CS 1 16 SCLK REF IN/REF OUT 2 15 DOUT V 3 14 DD DIN AGND 4 AD7888 13 AGND TOP VIEW AIN1 5 (Not to Scale) 12 AIN8 AIN2 6 11 AIN7 AIN3 7 10 AIN6 AIN4 8 9 AIN5 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function
1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7888 and also frames the serial data transfer. 2 REF IN/REF OUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external reference is from 1.2 V to VDD. 3 VDD Power Supply Input. The VDD range for the AD7888 is from 2.7 V to 5.25 V. 4, 13 AGND Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and any external reference signals should be referred to this AGND voltage. Both of these pins should connect to the AGND plane of a system. 5–12 AIN1–AIN8 Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0 through ADD2 bits of the Control Register. The input range for all input channels is 0 to VREF. Any unused input channels should be connected to AGND to avoid noise pickup. 14 DIN Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input and is clocked into the register on the rising edge of SCLK (see Control Register section). 15 DOUT Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. 16 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing serial data to the Control Register. This clock input is also used as the clock source for the AD7888’s conversion process. REV. C –5–