Datasheet AD7470, AD7472 (Analog Devices) - 7

AD7470/AD7472 PIN CONFIGURATIONS DB7 1 24 DB6 DB9 1 24 DB8 DB8 2 23 DB5 DB10 2 23 DB7 (MSB) DB9 3 22 DB4 (MSB) DB11 3 22 DB6 AV 4 21 DD VDRIVE AV 4 21 DD VDRIVE REF IN 5 20 DV REF IN 5 20 DV AD7470 DD AD7472 DD V 6 IN TOP VIEW 19 DGND V 6 IN TOP VIEW 19 DGND (Not to Scale) AGND 7 18 DB3 (Not to Scale) AGND 7 18 DB5 CS 8 17 DB2 CS 8 17 DB4 RD 9 16 DB1 RD 9 16 DB3 CONVST 10 15 DB0 (LSB) CONVST 10 15 DB2 CLKIN 11 14 NC CLKIN 11 14 DB1 BUSY 12 13 NC BUSY 12 13 DB0 (LSB) NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Mnemonic Function
CS Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired permanently low. RD Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently low, in which case the data bus is always active and the result of the new conversion is clocked out slightly before to the BUSY line going low. CONVST Conversion Start Input. Logic input used to initiate conversion. The input track-and-hold amplifier goes from track mode to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point. The conversion input can be as narrow as 10 ns. If the CONVST input is kept low for the duration of conversion and is still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep mode, the next rising edge of CONVST wakes up the part. Wake-up time for the part is typically 1 µs. CLK IN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7472 takes 14 clock cycles, and conversion time for the AD7470 takes 12 clock cycles. The frequency of this master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is not converting, the clock-in pad is in three-state and thus no clock is going through the part. BUSY BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after the falling edge of CONVST and stays high for the duration of conversion. Once conversion is complete and the con- version result is in the output register, the BUSY line returns low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, and the acquisition time for the part begins when BUSY goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY. REF IN Reference Input. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/ AD7472. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND. DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7470/ AD7472 aside from the output drivers. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND. AGND Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. REV. B –7– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track-and-Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Aperture Delay Aperture Jitter CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME Reference Input DC ACQUISITION TIME ANALOG INPUT CLOCK SOURCES PARALLEL INTERFACE OPERATING MODES Mode 1 (High Speed Sampling) Mode 2 (Sleep Mode) Burst Mode VDRIVE POWER-UP Power vs. Throughput Mode 1 Mode 2 Typical Performance Characteristics GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING AD7470/AD7472 to ADSP-2185 Interface AD7470/AD7472 to ADSP-21065 Interface AD7470/AD7472 to TMS320C25 Interface AD7470/AD7472 to PIC17C4x Interface AD7470/AD7472 to 80C186 Interface OUTLINE DIMENSIONS Revision History