Datasheet AD10200 (Analog Devices)

FabricanteAnalog Devices
DescripciónDual Channel, 12-Bit, 105 MSPS IF Sampling A/D Converter With Analog Input Signal Conditioning
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RevisiónB
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Idioma del documentoInglés

Dual Channel, 12-Bit 105 MSPS IF Sampling. A/D Converter with Analog Input. Signal Conditioning. AD10200. FEATURES

Datasheet AD10200 Analog Devices, Revisión: B

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Dual Channel, 12-Bit 105 MSPS IF Sampling
a
A/D Converter with Analog Input Signal Conditioning AD10200 FEATURES
includes two wide-dynamic range ADCs. Each ADC has a
Dual, 105 MSPS Minimum Sample Rate
transformer coupled front-end optimized for Direct-IF sampling.
Channel-Channel Isolation, >80 dB
The AD10200 has on-chip track-and-hold circuitry, and utilizes
AC-Coupled Signal Conditioning Included
an innovative architecture to achieve 12-bit, 105 MSPS perfor-
Gain Flatness up to Nyquist: < 0.2 dB
mance. The AD10200 uses innovative high-density circuit
Input VSWR 1.1:1 to Nyquist
design to achieve exceptional matching and performance while
80 dB Spurious-Free Dynamic Range
still maintaining excellent isolation, and providing for significant
Two’s Complement Output Format
board area savings.
3.3 V or 5 V CMOS-Compatible Output Levels
The AD10200 operates with 5.0 V supply for the analog-to-
0.850 W per Channel
digital conversion. Each channel is completely independent
Industrial and Military Grade
allowing operation with independent encode and analog inputs.
APPLICATIONS
The AD10200 is packaged in a 68-lead ceramic chip carrier
Radar IF Receivers
package. Manufacturing is done on Analog Devices, Inc. MIL-
Phased Array Receivers
38534 Qualified Manufacturers Line (QML) and components
Communications Receivers
are available up to Class-H (–50°C to +125°C).
Secure Communications GPS Antijamming Receivers PRODUCT HIGHLIGHTS Multichannel, Multimode Receivers
1. Guaranteed sample rate of 105 MSPS. 2. Input signal conditioning with full power bandwidth to
PRODUCT DESCRIPTION
250 MHz. The AD10200 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and 3. Fully tested/characterized performance at 121 MHz AIN. fully matched channel-to-channel performance. The module 4. Optimized for IF sampling.
FUNCTIONAL BLOCK DIAGRAM AINA2 AINB2 7 63 D00A 34 50 D00B (LSB) (LSB) D01A 33 49 D01B T1A T1B D02A 32 48 D02B D03A 31 47 D03B 50

50

D04A 30 46 D04B T/H T/H D05A AD10200 29 45 D05B 28 42 D06A D06B D07A 25 41 ADC ADC D07B D08A 24 40 D08B 12 12 12 12 D09A 23 39 D09B D10A 22 38 OUTPUT RESISTORS OUTPUT RESISTORS D10B D11A 21 37 D11B (MSB) (MSB) TIMING REF REF TIMING 18 17 3 56 53 54 ENCODEA ENCODEA REF_A_OUT REF_B_OUT ENCODEB ENCODEB
REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
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