Datasheet AD7899 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 5 V Single Supply 14-Bit 400 kSPS ADC |
| Páginas / Página | 17 / 5 — AD7899. TIMING CHARACTERISTICS1, 2 (VDD = 5 V |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 276 Kb |
| Idioma del documento | Inglés |
AD7899. TIMING CHARACTERISTICS1, 2 (VDD = 5 V
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AD7899 TIMING CHARACTERISTICS1, 2 (VDD = 5 V
ⴞ
5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN to TMAX and valid for VDRIVE = 3 V
ⴞ
5% and 5 V
ⴞ
5% unless otherwise noted.) A, B and S Parameter Versions Unit Test Conditions/Comments
tCONV 2.2 µs max Conversion Time, Internal Clock 2.46 µs max CLKIN = 6.5 MHz tACQ 0.3 µs max Acquisition Time tEOC 120 ns min EOC Pulsewidth 180 ns max t 5 WAKE-UP – External VREF 2 µs max STBY Rising Edge to CONVST Rising Edge (See Standby Mode Operation) t1 35 ns min CONVST Pulsewidth t2 70 ns min CONVST Rising Edge to BUSY Rising Edge Read Operation t3 0 ns min CS to RD Setup Time t4 0 ns min CS to RD Hold Time t5 35 ns min Read Pulsewidth t 3 6 35 ns max Data Access Time after Falling Edge of RD, VDRIVE = 5 V 40 ns max Data Access Time after Falling Edge of RD, VDRIVE = 3 V t 4 7 5 ns min Bus Relinquish Time after Rising Edge of RD 30 ns max t8 0 ns min BUSY Falling Edge to RD Delay External Clock t9 0 ns min CLKIN to CONVST Rising Edge Setup Time t10 20 ns min CLKIN to CONVST Rising Edge Hold Time t11 100 ns min CONVST Rising Edge to CLK Falling Edge NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of VDRIVE) and timed from a voltage level of VDRIVE/2. 2 See Figures 5, 6, 7, and 8. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5 Refer to the Standby Mode Operation section. Specifications subject to change without notice.
1.6mA TO OUTPUT 1.6V PIN 50pF 400
A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. A
ⴞ
5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; All specifications TMIN to TMAX and valid for VDRIVE = 3 V
ⴞ
5% and 5 V
ⴞ
5% unless otherwise noted.) A, B and S Parameter Versions Unit Test Conditions/Comments
tCONV 2.2 µs max Conversion Time, Internal Clock 2.46 µs max CLKIN = 6.5 MHz tACQ 0.3 µs max Acquisition Time tEOC 120 ns min EOC Pulsewidth 180 ns max t 5 WAKE-UP – External VREF 2 µs max STBY Rising Edge to CONVST Rising Edge (See Standby Mode Operation) t1 35 ns min CONVST Pulsewidth t2 70 ns min CONVST Rising Edge to BUSY Rising Edge Read Operation t3 0 ns min CS to RD Setup Time t4 0 ns min CS to RD Hold Time t5 35 ns min Read Pulsewidth t 3 6 35 ns max Data Access Time after Falling Edge of RD, VDRIVE = 5 V 40 ns max Data Access Time after Falling Edge of RD, VDRIVE = 3 V t 4 7 5 ns min Bus Relinquish Time after Rising Edge of RD 30 ns max t8 0 ns min BUSY Falling Edge to RD Delay External Clock t9 0 ns min CLKIN to CONVST Rising Edge Setup Time t10 20 ns min CLKIN to CONVST Rising Edge Hold Time t11 100 ns min CONVST Rising Edge to CLK Falling Edge NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of VDRIVE) and timed from a voltage level of VDRIVE/2. 2 See Figures 5, 6, 7, and 8. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 5 Refer to the Standby Mode Operation section. Specifications subject to change without notice.
1.6mA TO OUTPUT 1.6V PIN 50pF 400
A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time –4– REV. A