Datasheet AD9218 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| Páginas / Página | 29 / 8 — AD9218. SAMPLE. N + 1. N + 2. N + 7. N + 8. AINA. AINB. SAMPLE SAMPLE … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 887 Kb |
| Idioma del documento | Inglés |
AD9218. SAMPLE. N + 1. N + 2. N + 7. N + 8. AINA. AINB. SAMPLE SAMPLE SAMPLE SAMPLE. N + 3. N + 4. N + 5. N + 6. tEH. 1/fS. ENCODE A. tPD. ENCODE B
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AD9218 SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCODE A tPD tV ENCODE B D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
03 0 1-
D9B TO D0B DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
00 02 Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCODE A tPD tV ENCODE B D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
04 0 1-
D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
00 02 Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing Rev. C | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9218 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER SELECT OPTIONS APPLICATION INFORMATION AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE
03 0 1-
D9B TO D0B DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
00 02 Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE N N + 1 N + 2 SAMPLE N + 7 SAMPLE N + 8 AINA AINB t SAMPLE SAMPLE SAMPLE SAMPLE A t N + 3 N + 4 N + 5 N + 6 EL tEH 1/fS ENCODE A tPD tV ENCODE B D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
04 0 1-
D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
00 02 Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing Rev. C | Page 7 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9218 ENCODE INPUT DIGITAL OUTPUTS ANALOG INPUT VOLTAGE REFERENCE TIMING USER SELECT OPTIONS APPLICATION INFORMATION AD9218/AD9288 CUSTOMER PCB BOM EVALUATION BOARD POWER CONNECTOR ANALOG INPUTS VOLTAGE REFERENCE CLOCKING DATA OUTPUTS DATA FORMAT/GAIN TIMING TROUBLESHOOTING OUTLINE DIMENSIONS ORDERING GUIDE