Datasheet AD7783 (Analog Devices) - 3

AD7783–SPECIFICATIONS1 (VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.) Parameter AD7783B Unit Test Conditions
ADC CHANNEL SPECIFICATION Output Update Rate 19.79 Hz nom ADC CHANNEL No Missing Codes2 24 Bits min Resolution 16 Bits p-p ±160 mV Range, RANGE = 0 18 Bits p-p ±2.56 V Range, RANGE = 1 Output Noise See Table I 2 ¥ 1 024 . REFIN Integral Nonlinearity ±10 ppm of FSR max Typically 2 ppm, FSR = Gain Offset Error ±3 mV typ AIN(+) = AIN(–) = 2.5 V Offset Error Drift versus Temperature ±10 nV/∞C typ Full-Scale Error ±10 mV typ VDD = 3 V Gain Drift versus Temperature ±0.5 ppm/∞C typ Power Supply Rejection (PSR) 100 dB typ Input Range = ± 160 mV, VIN = 1/16 V 85 dB typ Input Range = ± 2.56 V, VIN = 1 V ANALOG INPUTS Differential Input Voltage Ranges ±160 mV nom Range = 0 ±2.56 V nom Range = 1 ADC Range Matching ±2 mV typ Input Voltage = 159 mV on Both Ranges Absolute AIN Voltage Limits GND + 100 mV V min VDD – 100 mV V max Analog Input Current2 DC Input Current ±1 nA max DC Input Current Drift ±5 pA/∞C typ Normal-Mode Rejection2, 3 @ 50 Hz 60 dB min 50 Hz ± 1 Hz @ 60 Hz 94 dB min 60 Hz ± 1 Hz Common-Mode Rejection Input Range = ± 160 mV, VIN = 1/16 V @ DC 105 dB min 125 dB typ, 110 dB typ when Input Range = ± 2.56 V @ 50 Hz2 100 dB min 50 Hz ± 1 Hz @ 60 Hz2 100 dB min 60 Hz ± 1 Hz REFERENCE INPUT REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–) REFIN Voltage Range2 1 V min VDD V max Absolute REFIN Voltage Limits2 GND – 30 mV V min VDD + 30 mV V max Average Reference Input Current 0.5 mA/V typ Average Reference Input Current Drift ±0.01 nA/V/∞C typ Normal-Mode Rejection2, 3 @ 50 Hz 60 dB min 50 Hz ± 1 Hz @ 60 Hz 94 dB min 60 Hz ± 1 Hz Common-Mode Rejection Input Range = ± 160 mV, VIN = 1/16 V @ DC 100 dB typ @ 50 Hz 110 dB typ 50 Hz ± 1 Hz @ 60 Hz 110 dB typ 60 Hz ± 1 Hz EXCITATION CURRENT SOURCES (IEXC1, IEXC2) Output Current 200 mA Initial Tolerance at 25∞C ±10 % typ Drift 200 ppm/∞C typ Initial Current Matching at 25∞C ±2.5 % max No Load Drift Matching 20 ppm/∞C typ Line Regulation 2.5 mA/V max VDD = 5 V ± 5%. Typically 1.25 mA/V. Load Regulation 300 nA/V typ Output Compliance VDD – 0.6 V max GND – 30 mV V min –2– REV. C Document Outline FEATURES INTERFACE POWER ON-CHIP FUNCTIONS APPLICATIONS FUNCTIONAL BLOCK DIAGRAM BASIC CONNECTION DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics ADC CIRCUIT INFORMATION Overview NOISE PERFORMANCE DIGITAL INTERFACE MASTER MODE (MODE = 0) SLAVE MODE (MODE = 1) CIRCUIT DESCRIPTION Analog Input Channel Programmable Gain Amplifier Bipolar Configuration/Output Coding Excitation Currents Crystal Oscillator Reference Input Grounding and Layout OUTLINE DIMENSIONS Revision History