Datasheet AD9433 (Analog Devices)

12-Bit, 105 MSPS/125 MSPS, IF Sampling ADC AD9433 FEATURES FUNCTIONAL BLOCK DIAGRAM IF sampling up to 350 MHz VCC AD9433 VDD SNR: 67.5 dB, fIN up to Nyquist at 105 MSPS SFDR: 83 dBc, fIN = 70 MHz at 105 MSPS AIN 12 PIPELINE T/H SFDR: 72 dBc, f 12 IN = 150 MHz at 105 MSPS ADC OUTPUT AIN STAGING D11 TO D0 2 V p-p analog input range On-chip clock duty cycle stabilization ENCODE ENCODE REF DFS On-chip reference and track-and-hold TIMING ENCODE SFDR SFDR optimization circuit MODE
01 0 7-
Excellent linearity
97
GND VREFOUT VREFIN
01
DNL: ±0.25 LSB (typical)
Figure 1.
INL: ±0.5 LSB (typical)
A user-selectable, on-chip proprietary circuit optimizes
750 MHz full power analog bandwidth
spurious-free dynamic range (SFDR) vs. signal-to-noise and
Power dissipation: 1.35 W (typical) at 125 MSPS
distortion (SINAD) ratio performance for different input signal
Twos complement or offset binary data format
frequencies, providing as much as 83 dBc SFDR performance
5.0 V analog supply operation
over the dc to 70 MHz band.
2.5 V to 3.3 V TTL/CMOS outputs
The encode clock supports either differential or single-ended
APPLICATIONS
input and is PECL-compatible. The output format is user-
Cellular infrastructure communication systems
selectable for offset binary or twos complement and provides
3G single- and multicarrier receivers
an overrange (OR) signal.
IF sampling schemes
Fabricated on an advanced BiCMOS process, the AD9433 is
Wideband carrier frequency systems
available in a 52-lead thin quad flat package (TQFP_EP) that
Point-to-point radios
is specified over the industrial temperature range of −40°C to
LMDS, wireless broadband
+85°C. The AD9433 is pin-compatible with the AD9432.
MMDS base station units Cable reverse path PRODUCT HIGHLIGHTS Communications test equipment
1. IF Sampling.
Radar and satellite ground systems
The AD9433 maintains outstanding ac performance up to input frequencies of 350 MHz. Suitable for 3G wideband
GENERAL INTRODUCTION
cellular IF sampling receivers. The AD9433 is a 12-bit, monolithic sampling analog-to-digital 2. Pin-Compatibility with the AD9432. converter (ADC) with an on-chip track-and-hold circuit and is The AD9433 has the same footprint and pin layout as the designed for ease of use. The product operates up to a 125 MSPS AD9432 12-bit 80 MSPS/105 MSPS ADC. conversion rate and is optimized for outstanding dynamic per- 3. SFDR Performance. formance in wideband and high IF carrier systems. A user-selectable, on-chip circuit optimizes SFDR The ADC requires a 5 V analog power supply and a differential performance as much as 83 dBc from dc to 70 MHz. encode clock for full performance operation. No external refer- 4. Sampling Rate. ence or driver components are required for many applications. At 125 MSPS, the AD9433 is ideally suited for wireless and The digital outputs are TTL-/CMOS-compatible, and a separate wired broadband applications such as LMDS/MMDS and output power supply pin supports interfacing with 3.3 V or cable reverse path. 2.5 V logic.
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Document Outline FEATURES APPLICATIONS GENERAL INTRODUCTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY EQUIVALENT CIRCUITS THEORY OF OPERATION ENCODE INPUT ENCODE VOLTAGE LEVEL DEFINITION ANALOG INPUT SFDR OPTIMIZATION DIGITAL OUTPUTS VOLTAGE REFERENCE TIMING APPLICATIONS INFORMATION LAYOUT INFORMATION REPLACING THE AD9432 WITH THE AD9433 OUTLINE DIMENSIONS ORDERING GUIDE