Datasheet AD7866 (Analog Devices) - 8

AD7866 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Mnemonic Function
11 RANGE Analog Input Range and Output Coding Selection. Logic input. The polarity on this pin will determine what input range the analog input channels on the AD7866 will have, and will also select the type of output coding the ADC will use for the conversion result. On the falling edge of CS, the polarity of this pin is checked to determine the analog input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF and the output coding from the part will be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes low, the analog input range is 2 VREF and the output coding for the part will be twos complement. How- ever, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth SCLK falling edge, the output coding will change to the other option without any change in the analog input range. (See the Analog Input and ADC Transfer Function sections.) 12 AVDD Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7866. The AVDD and DVDD voltages ideally should be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND. 13 DVDD Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7866. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND. 14 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart even on a transient basis. 15, 16 DOUTA, DOUTB Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously from the simultaneous conversions of both ADCs. The data stream consists of one leading zero followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for another 16 SCLK cycles after the conversion data has been output on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB alone using only one serial port. See the Serial Interface section. 17 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will operate. This pin should be decoupled to DGND. 18 SCLK Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7866. This clock is also used as the clock source for the conversion process. 19 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7866 and frames the serial data transfer. 20 A0 Multiplexer Select. Logic input. This input is used to select the pair of channels to be converted simultaneously, i.e., Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state of this pin is checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. If it is low, the following conversion will be performed on Channel 1 of each ADC; if it is high, the following conversion will be performed on Channel 2 of each ADC. REV. A –7– Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Positive Gain Error Negative Gain Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio (SNDR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation PSR (Power Supply Rejection) PERFORMANCE CURVES Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT Analog Input Ranges Handling Bipolar Input Signals Transfer Functions Digital Inputs REFERENCE CONFIGURATION OPTIONS MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7866 to ADSP-218x AD7866 to TMS320C541 AD7866 to DSP-563xx APPLICATION HINTS Grounding and Layout Evaluating the AD7866 Performance OUTLINE DIMENSIONS Revision History