Datasheet AD9430 (Analog Devices) - 10

AD9430 TIMING DIAGRAMS CLK+ CLK– DS+ DS– tSDS tHDS tPD 14 CYCLES t INTERLEAVED DATA OUT V PORT A STATIC INVALID N N+2 DA11–DA0 PORT B STATIC INVALID INVALID N+1 N+3 DB11–DB0 PARALLEL DATA OUT PORT A DA11–DA0 STATIC INVALID INVALID N N+2 PORT B STATIC INVALID INVALID N+1 N+3 DB11–DB0 tCPD DCO– STATIC DCO+
02607-002 Figure 2. CMOS Timing Diagram
N–1 N A N+1 IN tEL tEH 1/fS CLK+ CLK– tPD N–14 N–13 N N+1 DATA OUT 14 CYCLES DCO+ DCO–
02607-003
tCPD
Figure 3. LVDS Timing Diagram Rev. E | Page 9 of 44 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION APPLICATIONS TABLE OF CONTENTS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY APPLICATION NOTES THEORY OF OPERATION ENCODE INPUT ANALOG INPUT DS INPUTS (DS+, DS–) CMOS OUTPUTS LVDS OUTPUTS VOLTAGE REFERENCE NOISE POWER RATIO TESTING (NPR) EVALUATION BOARD, CMOS MODE POWER CONNECTOR ANALOG INPUTS GAIN ENCODE VOLTAGE REFERENCE DATA FORMAT SELECT I/P TIMING SELECT TIMING CONTROLS CMOS DATA OUTPUTS CRYSTAL OSCILLATOR OPTIONAL AMPLIFIER TROUBLESHOOTING EVALUATION BOARD, LVDS MODE POWER CONNECTOR ANALOG INPUTS GAIN CLOCK VOLTAGE REFERENCE DATA FORMAT SELECT DATA OUTPUTS CRYSTAL OSCILLATOR OUTLINE DIMENSIONS ORDERING GUIDE