Datasheet AD7485 (Analog Devices) - 9

AD7485 0 0 fIN = 10.7kHz fIN = 507.3kHz SNR = 78.76dB SNR = 78.35dB –20 SNR + D = 78.70dB –20 SNR + D = 78.33dB THD = –97.10dB THD = –100.33dB –40 –40 –60 –60 dB dB –80 –80 –100 –100 –120 –120 –140 –140 0 100 200 300 400 500 0 100 200 300 400 500 FREQUENCY – kHz FREQUENCY – kHz
TPC 7. 64k FFT Plot with 10 kHz Input Tone TPC 8. 64k FFT Plot with 500 kHz Input Tone
+VS
Figure 1 shows the analog input circuit used to obtain the data
8 1k 100
for the FFT plot shown in TPC 7. The circuit uses an Analog
AC 7 3 + SIGNAL
Devices AD829 op amp as the input buffer. A bipolar analog
1k 6 BIAS AD829 VIN
signal is applied as shown and biased up with a stable, low noise
VOLTAGE 4 2 – 5
dc voltage connected to the labeled terminal shown. A 220 pF
1 –VS
compensation capacitor is connected between Pin 5 of the AD829
220pF
and the analog ground plane. The AD829 is supplied with +12 V
150
and –12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and 10 µF capacitor Figure 1. Analog Input Circuit Used for 10 kHz Input Tone connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two capacitors to the device. More information on the AD829 is available on the Analog Devices website. For higher input bandwidth applications, Analog Devices’ AD8021 op amp (also available as a dual AD8022) is the recommended
+VS
choice to drive the AD7485. Figure 2 shows the analog input circuit used to obtain the data for the FFT plot shown in TPC 8.
8 50 AC
A bipolar analog signal is applied to the terminal shown and
2 7 + SIGNAL
biased with a stable, low noise dc voltage connected as shown. A
6 AD8021 VIN 220 BIAS
10 pF compensation capacitor is connected between Pin 5 of the
4 – VOLTAGE 3 5
AD8021 and the negative supply. As with the previous circuit,
1
the AD8021 is supplied with +12 V and –12 V supplies. The
10pF
supply pins are decoupled as close to the device as possible with
–VS
both a 0.1 µF and 10 µF capacitor connected to each pin. In each
220
case, the 0.1 µF capacitor should be the closer of the two capaci- tors to the device. The AD8021 Logic Reference pin is tied to
10pF
analog ground and the DISABLE pin is tied to the positive sup- Figure 2. Analog Input Circuit Used for 500 kHz Input Tone ply as shown. Detailed information on the AD8021 is available on the Analog Devices website. –8– REV. A Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Track/Hold Acquisition Time Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Typical Performance Characteristics CIRCUIT DESCRIPTION CONVERTER OPERATION ADC TRANSFER FUNCTION POWER SAVING SERIAL INTERFACE Driving the CONVST Pin Board Layout and Grounding OUTLINE DIMENSIONS