Datasheet AD7738 (Analog Devices) - 8

AD7738 PIN CONFIGURATION SCLK 1 28 DGND MCLKIN 2 27 DVDD MCLKOUT 3 26 DIN 4 25 CS DOUT 5 24 RESET RDY AV 6 23 DD AGND AD7738 AINCOM/P0 7 TOP VIEW 22 REFIN(–) (Not to Scale) 8 21 SYNC/P1 REFIN(+) AIN7 9 20 AIN0 AIN6 10 19 AIN1 AIN5 11 18 AIN2 AIN4 12 17 AIN3 MUXOUT(+) 13 16 ADCIN(+) MUXOUT(–) 14 15 ADCIN(–) PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description
1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7738. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected. 3 MCLKOUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to lower the device power consumption. MCLKOUT is capable of driving one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7738 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt-Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AVDD Analog Positive Supply Voltage. 5 V to AGND nominal. 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The pin is determined by the P0 Dir bit; the digital value can be written as the P0 bit in the I/O Port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 Dir bit set to 1), the single-ended Analog Inputs 0 to 7 can be referenced to this pin’s voltage level. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 Dir bit; the digital value can be read/written as the P1 bit in the I/O Port register. When the SYNC Enable bit in the I/O Port register is set to 1, the SYNC/P1 pin can be used to synchronize the AD7738 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low. 9–12, AIN0–AIN7 Analog Inputs 17–20 13 MUXOUT(+) Analog Multiplexer Positive Output 14 MUXOUT(–) Analog Multiplexer Negative Output REV. 0 –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS