Datasheet AD7732 (Analog Devices) - 4

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AD7732 AD7732—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V; REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comments
ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate 372 12190 Hz Configure via Conv. Time Register No Missing Codes1, 2 24 Bits FW ≥ 6 (Conversion Time ≥ 165 μs) Output Noise See Table 4 Resolution See Table 5 and Table 6 Integral Nonlinearity (INL) 1, 2, 3 ±0.0003 ±0.0015 % of FSR fMCLKIN = 2.5 MHz, VCM = 0 V Integral Nonlinearity (INL) 2, 3 ±0.0010 ±0.0030 % of FSR fMCLKIN = 6.144 MHz, VCM = 0 V Offset Error (Unipolar, Bipolar)4 ±13 mV Before Calibration Offset Drift vs. Temperature1 ±2.5 μV/°C Gain Error3 ±0.7 % Before Calibration Gain Drift vs. Temperature1 ±3.2 ppm of FS/°C Positive Full-Scale Error4 ±0.7 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp.1 ±3 ppm of FS/°C Bipolar Negative Full-Scale Error5 ±0.0060 % of FSR After Calibration Common-Mode Rejection 50 65 dB At DC Power Supply Sensitivity ±4 ±10 LSB16 At DC, AIN = 7 V, AVDD = 5 V ± 5% Channel-to-Channel Isolation 110 dB At DC, Maximum ±16.5 V AIN Voltage ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate 737 15437 Hz Configure via Conv. Time Register No Missing Codes1, 2 24 Bits FW ≥ 8 (Conversion Time ≥ 117 μs) Output Noise See Table 7 Resolution See Table 8 and Table 9 Integral Nonlinearity (INL) 2, 3 ±0.0015 % of FSR Offset Error (Unipolar, Bipolar)6 ±10 mV Before Calibration Offset Drift vs. Temperature ±25 μV/°C Gain Error4 ±0.5 % Before Calibration Gain Drift vs. Temperature ±5.3 ppm of FS/°C Positive Full-Scale Error4 ±0.5 % of FSR Before Calibration Positive Full-Scale Drift vs. Temp. ±4 ppm of FS/°C Bipolar Negative Full-Scale Error5 ±0.0060 % of FSR After Calibration Common-Mode Rejection 55 dB At DC Power Supply Sensitivity ±4 LSB16 At DC, AIN = 7 V, AVDD = 5 V ± 5% Channel-to-Channel Isolation 110 dB At DC, Maximum ±16.5 V AIN Voltage ANALOG INPUTS Analog Input Differential Voltage7 ±10 V Range ±10 V 0 V to +10 V Range 0 to +10 V ±5 V Range ±5 V 0 V to +5 V Range 0 to +5 V AIN Absolute Voltage1, 2, 8 –16.5 +16.5 V BIAS Voltage1 0 2.5 AVDD V RA, RB, RC, RD Voltage1 –10.5 +20 V AIN Impedance1, 9 100 124 kΩ AIN Pin Impedance1, 9 87.5 108.5 kΩ BIAS Pin Impedance1, 9 12.5 15.5 kΩ Rev. A | Page 3 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY AD7732—SPECIFICATIONS Table 1. (–40°C to +105°C; AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; BIAS (all), REFIN(+) = 2.5 V; REFIN(–) = AGND; RA, RB, RC, RD open circuit; AIN Range = ±10 V; fMCLKIN = 6.144 MHz; unless otherwise noted.) TIMING SPECIFICATIONS Table 2. (AVDD = 5 V ± 5%; DVDD = 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.) ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION Chopping Enabled Table 4. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Enabled Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Chopping Disabled Table 7. Typical Output RMS Noise in µV vs. Conversion Time and Input Range with Chopping Disabled Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Table 10. Pin Function Descriptions—28-Lead TSSOP REGISTER DESCRIPTION Table 11. Register Summary Table 12. Operational Mode Summary Table 13. Input Range Summary Register Access Communications Register Table 14. I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero-Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Table 15. Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7732 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Analog Input’s Extended Voltage Range Table 16. Extended Input Voltage Range, Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0 Table 17. Extended Input Voltage Range, Nominal Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0 Chopping Multiplexer, Conversion, and Data Output Timing Sigma-Delta ADC Frequency Response Voltage Reference Inputs Reference Detect I/O Port Calibration ADC Zero-Scale Self-Calibration Per Channel System Calibration High Common-Mode Voltage Application OUTLINE DIMENSIONS Ordering Guide