Datasheet AD7734 (Analog Devices) - 6

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Data Sheet AD7734 Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS AVDD–AGND Voltage 4.75 5.25 V DVDD–DGND Voltage 4.75 5.25 V 2.70 3.60 V AVDD Current (Normal Mode) 13.5 15.9 mA AVDD = 5 V DVDD Current (Normal Mode) 13 2.8 3.1 mA DVDD = 5 V DVDD Current (Normal Mode)13 1.0 1.5 mA DVDD = 3 V Power Dissipation (Normal Mode)13 85 100 mW AVDD+DVDD Current (Standby Mode)14 100 μA Power Dissipation (Standby Mode)14 525 μW 1 Specifications are not production tested but guaranteed by design and/or characterization data at initial product release. 2 See Typical Performance Characteristics. 3 Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 ADC zero-scale self-calibration reduces this error to ±10 mV. Channel zero-scale system calibration reduces this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for more details. 7 The adjacent channels are not affected by AIN voltage up to ±16.5 V. 8 Pin impedance is from the pin to the internal node. In normal circuit configuration, the analog input total impedance is typically 108.5 kΩ + 15.5 kΩ= 124 kΩ. 9 For specified performance. Device is functional with lower VREF. 10 Dynamic current charging the Σ-Δ modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. Rev. B | Page 5 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REGISTER DESCRIPTION REGISTER ACCESS COMMUNICATIONS REGISTER I/O PORT REGISTER REVISION REGISTER TEST REGISTER ADC STATUS REGISTER CHECKSUM REGISTER ADC ZERO-SCALE CALIBRATION REGISTER ADC FULL-SCALE REGISTER CHANNEL DATA REGISTERS CHANNEL ZERO-SCALE CALIBRATION REGISTERS CHANNEL FULL-SCALE CALIBRATION REGISTERS CHANNEL STATUS REGISTERS CHANNEL SETUP REGISTERS CHANNEL CONVERSION TIME REGISTERS MODE REGISTER DIGITAL INTERFACE DESCRIPTION HARDWARE RESET ACCESS THE AD7734 REGISTERS SINGLE CONVERSION AND READING DATA DUMP MODE CONTINUOUS CONVERSION MODE CONTINUOUS READ (CONTINUOUS CONVERSION) MODE CIRCUIT DESCRIPTION ANALOG FRONT END ANALOG INPUT’S EXTENDED VOLTAGE RANGE CHOPPING MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING Σ-Δ ADC FREQUENCY RESPONSE VOLTAGE REFERENCE INPUTS REFERENCE DETECT I/O PORT CALIBRATION ADC ZERO-SCALE SELF-CALIBRATION PER CHANNEL SYSTEM CALIBRATION OUTLINE DIMENSIONS ORDERING GUIDE