Datasheet AD7788, AD7789 (Analog Devices) - 9

Data Sheet AD7788/AD7789 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN AD7788/ CS 2 AD7789 9 DOUT/RDY AIN(+) 3 TOP VIEW 8 VDD (Not to Scale) AIN(–) 4 7 GND REFIN(+) 5 6 REFIN(–)
03539-005 Figure 5. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Description
1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous, with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the ADC in smaller batches of data. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. 3 AIN(+) Analog Input. AIN(+) is the positive terminal of the fully differential analog input. 4 AIN(−) Analog Input. AIN(–) is the negative terminal of the fully differential analog input. 5 REFIN(+) Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND + 0.1 V. The nominal reference voltage (REFIN(+) − REFIN(−)) is 2.5 V, but the device functions with a reference from 0.1 V to VDD. 6 REFIN(−) Negative Reference Input. This reference input can lie anywhere between GND and VDD − 0.1 V. 7 GND Ground Reference Point. 8 VDD Supply Voltage. 3 V or 5 V nominal. 9 DOUT/RDY The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated, but the RDY bit remains active. 10 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC; the register selection bits of the communications register identify the appropriate register. Rev. C | Page 9 of 20 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS SPECIFICATIONS AD7789 AD7788 AD7788/AD7789 TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) STATUS REGISTER (RS1, RS0 = 0, 0; Power-On/Reset = 0x88 for AD7788 and 0x8C for AD7789) MODE REGISTER (RS1, RS0 = 0, 1; Power-On/Reset = 0x02) DATA REGISTER (RS1, RS0 = 1, 1; Power-On/Reset = 0x0000 for the AD7788 and 0x000000 for the AD7789) ADC CIRCUIT INFORMATION NOISE PERFORMANCE DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE INPUT VDD MONITOR GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE NOTES