Datasheet AD7790 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 16-Bit, Single-Channel, Ultra Low Power, Sigma Delta A/D Converter |
| Páginas / Página | 21 / 7 — AD7790. Data Sheet. ISINK (1.6mA WITH VDD = 5V, 100. A WITH VDD = 3V). TO … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 471 Kb |
| Idioma del documento | Inglés |
AD7790. Data Sheet. ISINK (1.6mA WITH VDD = 5V, 100. A WITH VDD = 3V). TO OUTPUT. 1.6V. PIN. 50pF. ISOURCE (200. A WITH VDD = 5V, 100
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AD7790 Data Sheet ISINK (1.6mA WITH VDD = 5V, 100
µ
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
µ
A WITH VDD = 5V, 100
µ
A WITH VDD = 3V)
03538-0-002 Figure 2. Load Circuit for Timing Characterization
CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4
03538-0-003
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
03538-0-004
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20 Document Outline AD7790—Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88) Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02) Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04) Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Programmable Gain Amplifier Bipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Outline Dimensions Ordering Guide
µ
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
µ
A WITH VDD = 5V, 100
µ
A WITH VDD = 3V)
03538-0-002 Figure 2. Load Circuit for Timing Characterization
CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4
03538-0-003
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB
03538-0-004
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20 Document Outline AD7790—Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-on/Reset = 0x88) Mode Register (RS1, RS0 = 0, 1; Power-on/Reset = 0x02) Filter Register (RS1, RS0 = 1, 0; Power-on/Reset = 0x04) Data Register (RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Programmable Gain Amplifier Bipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Outline Dimensions Ordering Guide