Datasheet AD7440, AD7450A (Analog Devices) - 9

Data Sheet AD7440/AD7450A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 8 V DD 1 REF V 8 V AD7440/ REF 1 DD AD7440/ SCLK 2 7 VIN+ AD7450A V 7 SCLK IN+ 2 AD7450A SDATA 3 6 VIN– V 6 SDATA TOP VIEW IN– 3 TOP VIEW CS 4 (Not to Scale) 5 GND GND 4 (Not to Scale) 5 CS
03051-A-005 03051-A-006 Figure 5. Pin Configuration for 8-Lead SOT-23 Figure 6. Pin Configuration for 8-Lead MSOP
Table 5. Pin Function Descriptions Mnemonic Function
V Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the REF reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details. V Positive Terminal for Differential Analog Input. IN+ V Negative Terminal for Differential Analog Input. IN– GND Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external reference signal should be referred to this GND voltage. CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A and framing the serial data transfer. SDATA Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is twos complement. SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. V Power Supply Input. V is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 µF capacitor and DD DD a 10 µF tantalum capacitor in parallel. Rev. D | Page 9 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY AD7440–SPECIFICATIONS AD7450A–SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE GROUNDING AND LAYOUT HINTS EVALUATING THE AD7440/AD7450A PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE