Datasheet AD7441, AD7451 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | Pseudo Differential Input, 1 MSPS, 12-Bit ADC in an 8-Lead SOT-23 |
| Páginas / Página | 24 / 3 — AD7441/AD7451. SPECIFICATIONS. Table 1. AD7451 Parameter. Test … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 523 Kb |
| Idioma del documento | Inglés |
AD7441/AD7451. SPECIFICATIONS. Table 1. AD7451 Parameter. Test Conditions/Comments. A Version. B Version. Unit
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
AD7441/AD7451 SPECIFICATIONS
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature ranges for A, B versions: −40°C to +85°C.
Table 1. AD7451 Parameter Test Conditions/Comments A Version B Version Unit
DYNAMIC PERFORMANCE fIN = 100 kHz Signal-to-Noise Ratio (SNR)1 VDD = 2.7 V to 5.25 V 70 70 dB min Signal-to-(Noise + Distortion) (SINAD)1 VDD = 2.7 V to 3.6 V 69 69 dB min VDD = 4.75 V to 5.25 V 70 70 dB min Total Harmonic Distortion (THD)1 VDD = 2.7 V to 3.6 V; −78 dB typ −73 −73 dB max VDD = 4.75 V to 5.25 V; −80 dB typ −75 −75 dB max Peak Harmonic or Spurious Noise1 VDD = 2.7 V to 3.6 V; −80 dB typ −73 −73 dB max VDD = 4.75 V to 5.25 V; −82 dB typ −75 −75 dB max Intermodulation Distortion (IMD)1 fa = 90 kHz; fb = 110 kHz Second-Order Terms −80 −80 dB typ Third-Order Terms −80 −80 dB typ Aperture Delay1 5 5 ns typ Aperture Jitter1 50 50 ps typ Full-Power Bandwidth1, 2 @ −3 dB 20 20 MHz typ @ −0.1 dB 2.5 2.5 MHz typ DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity (INL)1 ±1.5 ±1 LSB max Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max Offset Error1 ±3.5 ±3.5 LSB max Gain Error1 ±3 ±3 LSB max ANALOG INPUT Full-Scale Input Span VIN+ − VIN– VREF VREF V Absolute Input Voltage VIN+ VREF VREF V V 3 IN– VDD = 2.7 V to 3.6 V −0.1 to +0.4 −0.1 to +0.4 V VDD = 4.75 V to 5.25 V −0.1 to +1.5 −0.1 to +1.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance When in track-and-hold 30/10 30/10 pF typ REFERENCE INPUT VREF Input Voltage4 ±1% tolerance for specified performance 2.5 2.5 V DC Leakage Current ±1 ±1 μA max VREF Input Capacitance When in track-and-hold 10/30 10/30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 ±1 μA max Input Capacitance, C 5 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA 2.8 2.8 V min VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA 2.4 2.4 V min Output Low Voltage, VOL ISINK = 200 μA 0.4 0.4 V max Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance5 10 10 pF max Output Coding Straight Straight (natural) binary (natural) binary Rev. D | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE Power-Up Time POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7441/AD7451 to ADSP-21xx AD7441/AD7451 to TMS320C5x/C54x AD7441/AD7451 to DSP56xxx GROUNDING AND LAYOUT HINTS EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7441/AD7451 SPECIFICATIONS
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature ranges for A, B versions: −40°C to +85°C.
Table 1. AD7451 Parameter Test Conditions/Comments A Version B Version Unit
DYNAMIC PERFORMANCE fIN = 100 kHz Signal-to-Noise Ratio (SNR)1 VDD = 2.7 V to 5.25 V 70 70 dB min Signal-to-(Noise + Distortion) (SINAD)1 VDD = 2.7 V to 3.6 V 69 69 dB min VDD = 4.75 V to 5.25 V 70 70 dB min Total Harmonic Distortion (THD)1 VDD = 2.7 V to 3.6 V; −78 dB typ −73 −73 dB max VDD = 4.75 V to 5.25 V; −80 dB typ −75 −75 dB max Peak Harmonic or Spurious Noise1 VDD = 2.7 V to 3.6 V; −80 dB typ −73 −73 dB max VDD = 4.75 V to 5.25 V; −82 dB typ −75 −75 dB max Intermodulation Distortion (IMD)1 fa = 90 kHz; fb = 110 kHz Second-Order Terms −80 −80 dB typ Third-Order Terms −80 −80 dB typ Aperture Delay1 5 5 ns typ Aperture Jitter1 50 50 ps typ Full-Power Bandwidth1, 2 @ −3 dB 20 20 MHz typ @ −0.1 dB 2.5 2.5 MHz typ DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity (INL)1 ±1.5 ±1 LSB max Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max Offset Error1 ±3.5 ±3.5 LSB max Gain Error1 ±3 ±3 LSB max ANALOG INPUT Full-Scale Input Span VIN+ − VIN– VREF VREF V Absolute Input Voltage VIN+ VREF VREF V V 3 IN– VDD = 2.7 V to 3.6 V −0.1 to +0.4 −0.1 to +0.4 V VDD = 4.75 V to 5.25 V −0.1 to +1.5 −0.1 to +1.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance When in track-and-hold 30/10 30/10 pF typ REFERENCE INPUT VREF Input Voltage4 ±1% tolerance for specified performance 2.5 2.5 V DC Leakage Current ±1 ±1 μA max VREF Input Capacitance When in track-and-hold 10/30 10/30 pF typ LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 V max Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 ±1 μA max Input Capacitance, C 5 IN 10 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA 2.8 2.8 V min VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA 2.4 2.4 V min Output Low Voltage, VOL ISINK = 200 μA 0.4 0.4 V max Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance5 10 10 pF max Output Coding Straight Straight (natural) binary (natural) binary Rev. D | Page 3 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT ANALOG INPUT STRUCTURE DIGITAL INPUTS REFERENCE SERIAL INTERFACE Timing Example 1 Timing Example 2 MODES OF OPERATION NORMAL MODE POWER-DOWN MODE Power-Up Time POWER VS. THROUGHPUT RATE MICROPROCESSOR AND DSP INTERFACING AD7441/AD7451 to ADSP-21xx AD7441/AD7451 to TMS320C5x/C54x AD7441/AD7451 to DSP56xxx GROUNDING AND LAYOUT HINTS EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE