Datasheet AD7652 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 16-Bit 500 kSPS PulSAR® Unipolar ADC with Ref |
| Páginas / Página | 29 / 6 — Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, … |
| Formato / tamaño de archivo | PDF / 804 Kb |
| Idioma del documento | Inglés |
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter. Symbol
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 20 link to page 20 link to page 20 link to page 21 link to page 21 link to page 22 link to page 22 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 7 link to page 23 link to page 23 link to page 6 link to page 6 link to page 11 AD7652 TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit
Refer to Figure 26 and Figure 27 Convert Pulsewidth t1 10 ns Time between Conversions t2 2 µs CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.25 µs Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.25 µs Acquisition Time t8 750 ns RESET Pulsewidth t9 10 ns Refer to Figure 28, Figure 29, and Figure 3 0 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 12 ns Bus Access Request to DATA Valid t12 45 ns Bus Relinquish Time t13 5 15 ns Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay1 t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t17 525 ns SYNC Asserted to SCLK First Edge Delay t18 3 ns Internal SCLK Period2 t19 25 40 ns Internal SCLK HIGH2 t20 12 ns Internal SCLK LOW2 t21 7 ns SDOUT Valid Setup Time2 t22 4 ns SDOUT Valid Hold Time2 t23 2 ns SCLK Last Edge to SYNC Delay2 t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert2 t28 See Table 4 CNVST LOW to SYNC Asserted Delay t29 1.25 µs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 34 and Figure 3 5 (Slave Serial Interface Modes)1 External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode. Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE SLAVE SERIAL INTERFACE MICROPROCESSOR INTERFACING APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES LAYOUT EVALUATING THE AD7652’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Symbol Min Typ Max Unit
Refer to Figure 26 and Figure 27 Convert Pulsewidth t1 10 ns Time between Conversions t2 2 µs CNVST LOW to BUSY HIGH Delay t3 35 ns BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.25 µs Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.25 µs Acquisition Time t8 750 ns RESET Pulsewidth t9 10 ns Refer to Figure 28, Figure 29, and Figure 3 0 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 12 ns Bus Access Request to DATA Valid t12 45 ns Bus Relinquish Time t13 5 15 ns Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay1 t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t17 525 ns SYNC Asserted to SCLK First Edge Delay t18 3 ns Internal SCLK Period2 t19 25 40 ns Internal SCLK HIGH2 t20 12 ns Internal SCLK LOW2 t21 7 ns SDOUT Valid Setup Time2 t22 4 ns SDOUT Valid Hold Time2 t23 2 ns SCLK Last Edge to SYNC Delay2 t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read after Convert2 t28 See Table 4 CNVST LOW to SYNC Asserted Delay t29 1.25 µs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figure 34 and Figure 3 5 (Slave Serial Interface Modes)1 External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns 1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode. Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE SLAVE SERIAL INTERFACE MICROPROCESSOR INTERFACING APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES LAYOUT EVALUATING THE AD7652’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE