Datasheet AD7787 (Analog Devices) - 9

AD7787 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SCLK 1 10 DIN CS 2 AD7787 9 DOUT/RDY AIN1(+) 3 TOP VIEW 8 VDD (Not to Scale) AIN1(–) 4 7 GND REFIN 5 6 AIN2
04477-0-005 Figure 5. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Function
1 SCLK Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted to or from the ADC in smaller batches of data. 2 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 3 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(−). 4 AIN1(–) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(−). 5 REFIN Reference Input. REFIN can be anywhere between VDD and GND + 0.1 V. The nominal reference voltage is 2.5 V, but the part functions with a reference from 0.1 V to VDD. 6 AIN2 Analog Input. AIN2 is a single-ended analog input. 7 GND Ground Reference Point. 8 VDD Supply Voltage, 2.5 V to 5.25 V. 9 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY pin is three-stated, but the RDY bit remains active. 10 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers within the ADC; the register selection bits of the communications register identifying the appropriate register. Rev. A | Page 8 of 20 Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide