Datasheet AD7685 (Analog Devices) - 7

FabricanteAnalog Devices
Descripción16-Bit, 250 kSPS PulSAR® ADC in MSOP/QFN
Páginas / Página29 / 7 — AD7685. Data Sheet. Table 5. VDD = 2.3V to 4.5 V1. Parameter. Symbol. …
RevisiónD
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AD7685. Data Sheet. Table 5. VDD = 2.3V to 4.5 V1. Parameter. Symbol. Min. Typ. Max. Unit. 70% VIO. 500µA. IOL. 30% VIO. tDELAY. TO SDO. 1.4V

AD7685 Data Sheet Table 5 VDD = 2.3V to 4.5 V1 Parameter Symbol Min Typ Max Unit 70% VIO 500µA IOL 30% VIO tDELAY TO SDO 1.4V

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AD7685 Data Sheet
−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 5. VDD = 2.3V to 4.5 V1 Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 µs Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 5 µs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36 ns 1 See Figure 3 and Figure 4 for load conditions.
70% VIO 500µA IOL 30% VIO tDELAY tDELAY TO SDO 1.4V 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 C 0.8V OR 0.5V2 0.8V OR 0.5V2 L 50pF NOTES
003
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
002
500µA IOH 2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
02968- 02968- Figure 3. Load Circuit for Digital Interface Timing Figure 4. Voltage Levels for Timing Rev. D | Page 6 of 28 Document Outline Features Applications Typical Application Circuit General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation Circuit Information Converter Operation Transfer Functions Typical Connection Diagram Analog Inputs Driver Amplifier Choice Voltage Reference Input Power Supply Supplying the ADC from the Reference Digital Interface CS/ Mode 3-Wire, No BUSY Indicator CS/ Mode 3-Wire with BUSY Indicator CS/ Mode 4-Wire, No BUSY Indicator CS/ Mode 4-Wire with BUSY Indicator Chain Mode, No BUSY Indicator Chain Mode with BUSY Indicator Application Hints Layout Evaluating the Performance of the AD7685 True 16-Bit Isolated Application Example Outline Dimensions Ordering Guide